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- 2024-3-28
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发表于 2021-4-16 15:58:57
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1. 主要看你是否使用了UART和elcdif的中断,如果使用中断方式会涉及到优先级的问题。
2. AT_NONECACHEABLE,从我们的cache 应用笔记中看,使用DMA的时候需要注意cache的问题,所以放到nocache也是可以的,另外还有以太网,SDHC需要注意nonecache的问题。
https://www.nxp.com/docs/en/application-note/AN12042.pdf
4.3.1. Use cacheable buffers
Normally buffers on the OCRAM, SDRAM are Cacheable and Write-Back. It can be in the stack, static section or allocated from heap. To use such buffer as DMA source, user must perform a DCACHE clean operation is done before DMA started, this makes sure all of the data are committed to the memory from cache. If buffer is used as DMA receive destination, a DCACHE invalidate operation must be done after DMA completed and before CPU or other masters read. The buffer address should be L1 cache line size aligned (32 bytes in i.MXRT).
3. 没有看到你的图3,可能上传失败了。
我估计和你一次传输的数据有关,具体你可以看下RM DMA的情况
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