LPC54101与jlink 连接下载调试需要注意什么？

anxb

焊接了个板子，死活连接下载不了程序。vcc gnd  复位端  SWDIO  SWCLK 都链接了，并且sw都有上下拉电阻，调试环境用IAR  ，是不是芯片锁死了？怎么判断呢？

我知道答案 目前已有10人回答

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mgn

能找到Chip的ID么？

anxb

Tue Apr 27, 2021 15:50:35: Found SWD-DP with ID 0x2BA01477
Tue Apr 27, 2021 15:50:35: AP-IDR: 0x00000000, Type: JTAG-AP
Tue Apr 27, 2021 15:50:35: Could not power-up debug power domain.
iar显示以上内容

jobszheng5

会不会楼主的jlink版本过于低导致的。
貌似要使用新一些的jlink v9

az158

可以看一下电源部分，看看芯片的供电是否正常

anxb

我用的jlink v9

小恩GG

能否进入ISP 模式， 用flash magic 试试。

anxb

和ISP管脚有关系吗？我悬空了，是不是必须接高电平？

anxb

找到问题了，我用MCUXpresso配置的代码，外部时钟12m，倍频到80M，
配置完的代码只要下载到单片机里面，运行后SW就链接不了，配置后的代码有问题。大家使用时谨慎。我到现在还没有找到哪里的问题

anxb

下面是代码，看看有什么问题吗


/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* How to set up clock using clock driver functions:
*
* 1. Setup clock sources.
*
* 2. Setup voltage for the fastest of the clock outputs
*
* 3. Set up wait states of the flash.
*
* 4. Set up all dividers.
*
* 5. Set up all selectors to provide selected clocks.
*/

/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v5.0
processor: LPC54101J256
package_id: LPC54101J256BD64
mcu_data: ksdk2_0
processor_version: 5.0.1
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */

#include "fsl_power.h"
#include "fsl_clock.h"
#include "clock_config.h"

/*******************************************************************************
* Definitions
******************************************************************************/

/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;

/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
}

/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
outputs:
- {id: ASYNCAPB_clock.outFreq, value: 40 MHz}
- {id: MAIN_clock.outFreq, value: 80 MHz}
- {id: System_clock.outFreq, value: 80 MHz, locked: true, accuracy: '0.001'}
settings:
- {id: PLL_Mode, value: Fractional}
- {id: ASYNC_SYSCON.ASYNCCLKDIV.scale, value: '2'}
- {id: SYSCON.DIRECTO.sel, value: SYSCON.PLL}
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
- {id: SYSCON.M_MULT.scale, value: '40960', locked: true}
- {id: SYSCON.N_DIV.scale, value: '3', locked: true}
- {id: SYSCON.PDEC.scale, value: '2', locked: true}
- {id: SYSCON.PLL_BYPASS.sel, value: SYSCON.DIRECTO}
- {id: SYSCON.SYSPLLCLKSEL.sel, value: SYSCON.clk_in}
sources:
- {id: SYSCON.clk_in.outFreq, value: 12 MHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */

/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
    /*!< Set up the clock sources */
    /*!< Set up IRC */
    POWER_DisablePD(kPDRUNCFG_PD_IRC_OSC);                   /*!< Ensure IRC OSC is on */
    POWER_DisablePD(kPDRUNCFG_PD_IRC);                       /*!< Ensure IRC is on */
    CLOCK_AttachClk(kIRC12M_to_MAIN_CLK);                    /*!< Switch to IRC 12MHz first to ensure we can change voltage without accidentally
                                                                  being below the voltage for current speed */

    /*!< Set up PLL */
    CLOCK_AttachClk(kCLKIN_to_SYS_PLL);                    /*!< Switch SYSPLLCLKSEL to CLKIN */
    POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL);                   /*!< Ensure PLL is on  */
    const pll_setup_t pllSetup = {
        .syspllctrl = SYSCON_SYSPLLCTRL_UPLIMOFF_MASK | SYSCON_SYSPLLCTRL_DIRECTO_MASK,
        .syspllndec = SYSCON_SYSPLLNDEC_NDEC(1U),
        .syspllpdec = SYSCON_SYSPLLPDEC_PDEC(98U),
        .syspllssctrl = {0x0U,(SYSCON_SYSPLLSSCTRL1_MD(20480U) | (uint32_t)(kSS_MF_512) | (uint32_t)(kSS_MR_K0) | (uint32_t)(kSS_MC_NOC))},
        .pllRate = 80000000U,
        .flags =  PLL_SETUPFLAG_POWERUP
    };
    CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired values */

    /* PLL in Fractional/Spread spectrum mode */
    /* SYSTICK is used for waiting for PLL stabilization */

    CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true);              /*!< Reset SysTick divider counter and halt it */
    CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 3U, false);             /*!< Set SysTick divider to value 3 */
    SysTick->LOAD = 27999UL;                              /*!< Set SysTick count value */
    SysTick->VAL = 0UL;                                           /*!< Reset current count value */
    SysTick->CTRL = SysTick_CTRL_ENABLE_Msk;                      /*!< Enable SYSTICK */
    while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != SysTick_CTRL_COUNTFLAG_Msk){}   /*!< Waiting 7ms for PLL stabilization */
    SysTick->CTRL = 0UL;                                          /*!< Stop SYSTICK */

    POWER_SetVoltageForFreq(80000000U);                      /*!< Set voltage for the one of the fastest clock outputs: System clock output */
    CLOCK_SetFLASHAccessCyclesForFreq(80000000U);            /*!< Set FLASH wait states for core */

    /*!< Set up dividers */
    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);              /*!< Set AHBCLKDIV divider to value 1 */
    SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE_MASK;   /*!< Enable ASYNC APB subsystem */
    Clock_SetAsyncClkDiv(2U);                  /*!< Set ASYNCCLKDIV divider to value 2 */

    /*!< Set up clock selectors - Attach clocks to the peripheries */
    CLOCK_AttachClk(kCLKIN_to_SYS_PLL);                      /*!< Switch SYS_PLL to CLKIN */
    CLOCK_AttachClk(kSYS_PLL_OUT_to_MAIN_CLK);                      /*!< Switch MAIN_CLK to SYS_PLL_OUT */

    /*< Set SystemCoreClock variable. */
    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}