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LL16.H库中LCD寄存器之二、LCD控制寄存器

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    [LV.1]初来乍到

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    发表于 2010-5-14 16:33:21 | 显示全部楼层 |阅读模式
     
     
     一、LCDC0主要包含:时钟分频、时钟设置、时钟源、使能开启



    1LCDC0_DUTY0-2LCD占空比选择。选择LCD模块驱动的占空比周期。
     2LCDC0_LCLK0-2LCD模块帧频率=LCDCLK/((DUTY+1) x 8 x (4 + LCLK[2:0]) x Y)
    备注:LCDCLK范围是30< LCDCLK < 39.063 kHzY = 2,2,3,3,4,5,8,16由模块占空比周期配置选择。
    3LCDC0_SOURCE LCD时钟源选择。LCD模块选择2个可能存在的时钟源。
       0:选择ICSERCLK(外部参考时钟)作为时钟源;
       1:选择预备时钟作为时钟源。
    4LCDC0_LCDEN  LCD驱动使能,LCDEN开始产生LCD波形。
    二、LCDC1 - LCD Control Register
    1LCDC1_LCDSTP:当在STOP23的模式下,是否停止LCD模块驱动和改变泵电压。
    2LCDC1_LCDWAI:在等待模式下,是否停止LCD模块驱动和改变泵电压。
    3LCDC1_FCDEN:完整补充驱动模式使能
    4LCDC1_LCDIENLCD模块驱动结构中断使能
    三、LCDSUPPLYLCD电源寄存器
    1LCDSUPPLY_VSUPPLY0-1LCD电源控制选择
     2LCDSUPPLY_LADJ0-1LCD模式负载调节。该位用于配置LCD模块处理不同LCD玻璃电容。
    3LCDSUPPLY_CPSEL:电荷泵或电阻器选择。  
    附录:LL16.H中的寄存器地址和寄存器各位说明 



    ;*** LCDC0 - LCD Control Register 0; 0x00000018 ***
    LCDC0:              equ    $00000018                                ;*** LCDC0 - LCD Control Register 0; 0x00000018 ***
    ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
    LCDC0_DUTY0:        equ    0                                         ; LCD Duty Select Bit 0
    LCDC0_DUTY1:        equ    1                                         ; LCD Duty Select Bit 1
    LCDC0_DUTY2:        equ    2                                         ; LCD Duty Select Bit 2
    LCDC0_LCLK0:        equ    3                                         ; LCD Clock Prescaler Bit 0
    LCDC0_LCLK1:        equ    4                                         ; LCD Clock Prescaler Bit 1
    LCDC0_LCLK2:        equ    5                                         ; LCD Clock Prescaler Bit 2
    LCDC0_SOURCE:       equ    6                                         ; LCD Clock Source Select
    LCDC0_LCDEN:        equ    7                                         ; LCD Driver Enable
    ; bit position masks
    mLCDC0_DUTY0:       equ    %00000001
    mLCDC0_DUTY1:       equ    %00000010
    mLCDC0_DUTY2:       equ    %00000100
    mLCDC0_LCLK0:       equ    %00001000
    mLCDC0_LCLK1:       equ    %00010000
    mLCDC0_LCLK2:       equ    %00100000
    mLCDC0_SOURCE:      equ    %01000000
    mLCDC0_LCDEN:       equ    %10000000
     

    ;*** LCDC1 - LCD Control Register 1; 0x00000019 ***
    LCDC1:              equ    $00000019                                ;*** LCDC1 - LCD Control Register 1; 0x00000019 ***
    ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
    LCDC1_LCDSTP:       equ    0                                         ; LCD Module Driver and Charge Pump Stop While in Stop2 or Stop3 Mode
    LCDC1_LCDWAI:       equ    1                                         ; LCD Module Driver and Charge Pump Stop While in Wait Mode
    LCDC1_FCDEN:        equ    2                                         ; Full Complementary Drive Enable
    LCDC1_LCDIEN:       equ    7                                         ; LCD Module Frame Frequency Interrupt Enable
    ; bit position masks
    mLCDC1_LCDSTP:      equ    %00000001
    mLCDC1_LCDWAI:      equ    %00000010
    mLCDC1_FCDEN:       equ    %00000100
    mLCDC1_LCDIEN:      equ    %10000000

    ;*** LCDSUPPLY - LCD Voltage Supply Register; 0x0000001A ***
    LCDSUPPLY:          equ    $0000001A                                ;*** LCDSUPPLY - LCD Voltage Supply Register; 0x0000001A ***
    ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
    LCDSUPPLY_VSUPPLY0: equ    0                                         ; Voltage Supply Control Bit 0
    LCDSUPPLY_VSUPPLY1: equ    1                                         ; Voltage Supply Control Bit 1
    LCDSUPPLY_BBYPASS:  equ    2                                         ; Op Amp Control
    LCDSUPPLY_LADJ0:    equ    4                                         ; LCD Module Load Adjust Bit 0
    LCDSUPPLY_LADJ1:    equ    5                                         ; LCD Module Load Adjust Bit 1
    LCDSUPPLY_HREFSEL:  equ    6                                         ; High Reference Select
    LCDSUPPLY_CPSEL:    equ    7                                         ; Charge Pump or Resistor Bias Select
    ; bit position masks
    mLCDSUPPLY_VSUPPLY0: equ    %00000001
    mLCDSUPPLY_VSUPPLY1: equ    %00000010
    mLCDSUPPLY_BBYPASS: equ    %00000100
    mLCDSUPPLY_LADJ0:   equ    %00010000
    mLCDSUPPLY_LADJ1:   equ    %00100000
    mLCDSUPPLY_HREFSEL: equ    %01000000
    mLCDSUPPLY_CPSEL:   equ    %10000000

    ;*** LCDRVC - LCD Regulated Voltage Control Register; 0x0000001B ***
    LCDRVC:             equ    $0000001B                                ;*** LCDRVC - LCD Regulated Voltage Control Register; 0x0000001B ***
    ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
    LCDRVC_RVTRIM0:     equ    0                                         ; Regulated Voltage Trim Bit 0
    LCDRVC_RVTRIM1:     equ    1                                         ; Regulated Voltage Trim Bit 1
    LCDRVC_RVTRIM2:     equ    2                                         ; Regulated Voltage Trim Bit 2
    LCDRVC_RVTRIM3:&
     
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    发表于 2015-11-16 14:14:09 | 显示全部楼层
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