TxBDs = (nbuf_t *)((uint32)(unaligned_tx_nbuf + 16) & 0xFFFFFFF0);
TxBuff = (uint8 *)((uint32)(unaligned_tx_buf + 16) & 0xFFFFFFF0);
/* Initialize receive descriptor ring */
for( i = 0; i < NUM_RXBDS; i++ )
{
RxBDs.status = RX_BD_E;
RxBDs.length = 0;
RxBDs.data = &RxBuff[i * RX_BUFFER_SIZE];
}
/* Set the Wrap bit on the last one in the ring */
RxBDs[NUM_RXBDS - 1].status |= RX_BD_W;
/* Initialize transmit descriptor ring */
for( i = 0; i < NUM_TXBDS; i++ )
{
TxBDs.status = 0 | TX_BD_L ;// | TX_BD_TC;
TxBDs.length = 0;
TxBDs.data = &TxBuff[0];/*FSL:workaround*///1520*i
}
/* Set the Wrap bit on the last one in the ring */
TxBDs[NUM_TXBDS - 1].status |= TX_BD_W;
/* Initialize the buffer descriptor indexes */
tx_bd_idx = rx_bd_idx = 0;
//return;
}
void FEC_ResetProcessing(const uint8 *pa)
{ unsigned int uuu;
// extern uint32 __VECTOR_RAM[];