关于7816demo中CLK设置问题

mscs13179 · 发表于 2015-1-20 15:58:27

本帖最后由 mscs13179 于 2015-1-20 16:16 编辑

void main (void)
{
unsigned int i,core_clk_mhz,periph_clk_mhz;
extern int mcg_clk_hz,core_clk_khz,periph_clk_khz;
#ifdef VLPR_TEST
int fast_irc_freq = 4000000;
/* auto trim internal fast IRC to 4MHz */
atc(FAST_IRC, fast_irc_freq, mcg_clk_hz);
/* PEE -> PBE */
mcg_clk_hz = pee_pbe(CLK0_FREQ_HZ);
/* PBE -> FBE */
mcg_clk_hz = pbe_fbe(CLK0_FREQ_HZ);
/* FBE -> FBI */
mcg_clk_hz = fbe_fbi(fast_irc_freq,FAST_IRC);
/* FBI -> BLPI */
mcg_clk_hz = fbi_blpi(fast_irc_freq,FAST_IRC);
SIM_CLKDIV1 = 0x00110000;
core_clk_khz = mcg_clk_hz/1000;
periph_clk_khz = core_clk_khz;
/* Change UART baud rate to 19200 under VLPR mode*/
uart_init (TERM_PORT, core_clk_khz, 19200);
printf("\n In blpi mode now ready for entry into VLPR \n\n");
enter_vlpr(0);
PORTC_PCR3 = ( PORT_PCR_MUX(1));
PORTA_PCR18 = PORT_PCR_MUX(4);//PTA18 as FTM_CLKIN0
#endif
core_clk_mhz = core_clk_khz/1000;
periph_clk_mhz = periph_clk_khz/1000;
//CPU =96M, Bus =48M
//init GPIO, refer to the Firebird Daughter card schematic
// SIM0_VEN - LCD_P33/PTC13/UART4_CTS
PORTC_PCR13 = PORT_PCR_MUX(1);
GPIOC_PDOR &= ~(SIM0_VEN_BIT); //VEN set as 0
GPIOC_PDDR |= (SIM0_VEN_BIT);
// SIM0_RST - LCD_P39/PTC19/UART3_CTS
PORTC_PCR19 = PORT_PCR_MUX(1);
GPIOC_PDOR &= ~(SIM0_RST_BIT); //reset set as 0
GPIOC_PDDR |= (SIM0_RST_BIT);
#ifndef VLPR_TEST// in VLPR mode , use FB_CLK for SIM_CLK
// SIM0_CLK - LCD_P46/PTD6/FTM0_CH6/FTM0_FLT0
PORTD_PCR6 = PORT_PCR_MUX(4);//FTM0
#endif
// SIM0_PD - LCD_P38/PTC18/UART3_RTS
PORTC_PCR18 = PORT_PCR_MUX(1);
GPIOC_PDDR &= ~(SIM0_PD_BIT);//GPIO input
// SIM0_DATA - LCD_P47/PTD7/CMT_IRO/_UART0_TX
PORTD_PCR7 = PORT_PCR_MUX(3);
//PORTB_PCR17 = PORT_PCR_MUX(3);
printf("\n Kinetis ISO7816 test \n");
if(SIM_PD)
printf("No Smart Card insert in slot 0\n");
while(SIM_PD);
printf("Smart Card inserted in slot 0\n");
#ifndef VLPR_TEST
//init the SIM clock, using FTM0_CH6
SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK;
FTM0_STATUS;
FTM0_STATUS = 0;
//prescale = 1, clock source = bus clock
FTM0_CNTIN = 0;
FTM0_C6SC = FTM_CnSC_MSA_MASK|FTM_CnSC_ELSA_MASK; //ELSB:ELSA= 0b01, MSB:MSA= 0b01 means output compare, tougle output on match
FTM0_C6V = 1;
FTM0_MOD = (periph_clk_mhz/2)/SIM_CLK -1; //generate 2MHz CLK
FTM0_MODE |= FTM_MODE_FTMEN_MASK;
FTM0_OUTMASK &= ~FTM_OUTMASK_CH6OM_MASK;
FTM0_SC = FTM_SC_PS(0)|
FTM_SC_CLKS(1);
#else
PORTC_PCR3 = ( PORT_PCR_MUX(0x5));
#endif
//init UART to ISO7816 format
//The SIM_CLK is 2MHz, so the baudrate is 2M/372
status = IDLE_STATE;
i = (uint16)((core_clk_mhz)*Fi/(SIM_CLK * 16));
// SIM_SOPT5 = SIM_SOPT5_UART0TXSRC(0)|SIM_SOPT5_UART0RXSRC(0);
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
UART0_BDH |= UART_BDH_SBR(((i & 0x1F00) >> 8));
UART0_BDL = (uint8)(i & UART_BDL_SBR_MASK);
#ifdef VLPR_TEST
UART0_C4 = 0x10; //refine the baudrate
#else
UART0_C4 = 0x00;
#endif
//printf("UART0_WP7816T1 = 0x%x\n",UART0_WP7816T1);
UART0_WP7816T0 = 1; UART0_WF7816 = 1;//set the WT = 960*1*1 =960 etu
// UART0_WP7816T0 = 1; UART0_WF7816 = 10;//set the WT = 960*1*10 =9600 etu
//UART0_C7816 |= UART_C7816_TTYPE_MASK;
//UART0_C7816 |= UART_C7816_ISO_7816E_MASK;
//printf("UART0_WP7816T1 = 0x%x\n",UART0_WP7816T1);
//one wire mode, 9bit mode, Even parity
UART0_C1 = UART_C1_LOOPS_MASK |
UART_C1_RSRC_MASK |
UART_C1_M_MASK |
// UART_C1_PT_MASK| //set Odd parity to see if the NACK error detect and retransfer
UART_C1_PE_MASK;
UART0_S2 = 0;
#ifdef INVERSE
UART0_S2 |= UART_S2_MSBF_MASK | UART_S2_RXINV_MASK; // inverse mode
#endif
UART0_MODEM = 0;
UART0_C3 |= (UART_C3_ORIE_MASK|UART_C3_NEIE_MASK|UART_C3_FEIE_MASK|UART_C3_PEIE_MASK);
#ifdef INVERSE
// UART0_C3 |= UART_C3_TXINV_MASK; //inverse mode
#endif
UART0_C4 &= ~(UART_C4_MAEN1_MASK|UART_C4_MAEN2_MASK);
UART0_C5 = 0;
UART0_C7816 = UART_C7816_INIT_MASK |
UART_C7816_ISO_7816E_MASK |
UART_C7816_ONACK_MASK |
UART_C7816_ANACK_MASK;
UART0_C2 = UART_C2_TE_MASK | UART_C2_RE_MASK;
#ifdef NACK_THRESHOLD_TEST
// UART0_PFIFO = UART_PFIFO_TXFE_MASK | UART_PFIFO_RXFE_MASK;
txt_cnt = 0;
rxt_cnt = 0;
i = 1;
UART0_ET7816 = (i<<4)|i;
#endif
// UART0_IE7816 |= (UART_IE7816_WTE_MASK|UART_IE7816_CWTE_MASK|UART_IE7816_BWTE_MASK|UART_IE7816_GTVE_MASK);
// UART0_IE7816 |= (UART_IE7816_WTE_MASK|UART_IE7816_GTVE_MASK);
#if 0
UART0_C3 |= UART_C3_TXDIR_MASK; //set the TX pin as output
UART0_TL7816 = 2; //the TLEN does not count the NAD, PCB, LEN, LRC, if use CRC, it should + 1
UART0_C2 |= UART_C2_TE_MASK; //enable TX
UART0_D = 0x55;
UART0_D = 0xaa;
#endif
if(ATR()!=0)
{
printf("ATR failed!\n");
goto exit0;
}
else
printf("ATR successfull!\n");
//T=0 transport
Trans_T0();
//T=1 transport
Trans_T1();
exit0:
while(1)
{
}
}

复制代码

以上是7816的demo中代码，对于以上代码的理解是
1、7816协议接口的clk由FTM产生；
2、根据代码中给定sysclk 【Bus Clock=48M】，由FTM0_SC的配置可以得到 FTM_CLK=sysclk/（2^0）;
又FTM0_CNT=0（默认为0）;FTM0_CNTIN=0;
PWM周期= （MOD - CNTIN+1)*FTM_CLK
这个和代码中注释的信息generate 2MHz CLK是否是有问题【备注不定义 VLPR_TEST】
即代码中MOD=(periph_clk_mhz/2)/SIM_CLK -1=48M/2/2 -1=12M-1 【其中#define SIM_CLK 2 //in MHz from FTM0_CH6】

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