【申请YL-KL26Z】+制做一个定时小闹钟

一花一世界003 · 发表于 2015-2-12 13:08:46

通过学习飞思卡尔ARM0系列的处理器特性，可以使用其按键中断设定闹钟时间，然后通过读取SD卡里面的WAV文件并且播放音乐，后期如果可以的话，因为要人性化一些，就必须要使用一个TFT模块来设定时间，所以也可以更好的学习KL的一些基本模块的特性。

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一花一世界003 · 发表于 2015-3-16 17:30:29

今天收到了板子，开始发一下我的学习加制作教程。
因为首先要涉及闹钟的时钟功能，所以我在mbed时间库里寻找，但是多少想直接使用IAR来开发---这样显得正式，所以就去看芯片提供的DEMO,就像是K60，一般有PIT,LPTMR,SIM,RTC,OSC,MCG现在ARM Cortex M0+ core resides within a synchronous core platform, where the processorand bus masters, flash memory, and peripheral clocks can be configured independently.
QQ截图20150316170709.png

下面这是系统时钟配置函数。首先是这2张图
QQ截图20150316171258.png

void SystemCoreClockUpdate (void) {
  uint32_t MCGOUTClock;                                                       /* Variable to store output clock frequency of the MCG module */
  uint8_t Divider;

  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
/* Output of FLL or PLL is selected */
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
   /* FLL is selected */
   if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
      /* External reference clock is selected */
      MCGOUTClock = CPU_XTAL_CLK_HZ;                                     /* System oscillator drives MCG clock */
      Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
      MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
      if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
      MCGOUTClock /= 32u;                                                 /* If high range is enabled, additional 32 divider is active */
      } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
   } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
      MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                  /* The slow internal reference clock is selected */
   } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
   /* Select correct multiplier to calculate the MCG output clock  */
   switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
      case 0x0u:
      MCGOUTClock *= 640u;
      break;
      case 0x20u:
      MCGOUTClock *= 1280u;
      break;
      case 0x40u:
      MCGOUTClock *= 1920u;
      break;
      case 0x60u:
      MCGOUTClock *= 2560u;
      break;
      case 0x80u:
      MCGOUTClock *= 732u;
      break;
      case 0xA0u:
      MCGOUTClock *= 1464u;
      break;
      case 0xC0u:
      MCGOUTClock *= 2197u;
      break;
      case 0xE0u:
      MCGOUTClock *= 2929u;
      break;
      default:
      break;
   }
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
   /* PLL is selected */
   Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
   MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider);                   /* Calculate the PLL reference clock */
   Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
   MCGOUTClock *= Divider;                      /* Calculate the MCG output clock */
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
   MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
   MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));  /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
/* External reference clock is selected */
MCGOUTClock = CPU_XTAL_CLK_HZ;                                        /* System oscillator drives MCG clock */
  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
/* Reserved value */
return;
  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
  SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}

然后是寄存器的读写，需要看的是---