KL-26Z的TSI

一花一世界003 · 发表于 2015-3-19 20:33:41

KL-46的TSI非常好用,手册上面这样介绍
The touch sensing input (TSI) module provides capacitive touch sensing detection with
high sensitivity and enhanced robustness. Each TSI pin implements the capacitive
measurement by a current source scan, charging and discharging the electrode, once or
several times.
大致就是TSI电容触摸感应探测有着高可靠性，原理是触摸触发那个不停的电极改变。
A reference oscillator ticks the scan
time and stores the result in a 16-bit register when the scan completes. Meanwhile, an
interrupt request is submitted to CPU for post-processing if TSI interrupt is enabled and
DMA function is not selected.The TSI module can be periodically triggered to work in
low power mode with ultra-low current adder and wake CPU at the end of scan or the
conversion result is out of the range specified by TSI threshold. It provides a solid
capacitive measurement module to the implementation of touch keyboard, rotaries and

sliders.

先学习一下它的宏定义
typedef struct TSI_MemMap {
  uint32_t GENCS;                               /**< TSI General Control and Status Register, offset: 0x0 */
  uint32_t DATA;                                  /**< TSI DATA Register, offset: 0x4 */
  uint32_t TSHD;                                  /**< TSI Threshold Register, offset: 0x8 */
} volatile *TSI_MemMapPtr;

/* ----------------------------------------------------------------------------
-- TSI - Register accessor macros
---------------------------------------------------------------------------- */

/**
* @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros
* @{
*/

/* TSI - Register accessors */
#define TSI_GENCS_REG(base)                   ((base)->GENCS)
#define TSI_DATA_REG(base)                      ((base)->DATA)
#define TSI_TSHD_REG(base)                      ((base)->TSHD)

/**
* @}
*/ /* end of group TSI_Register_Accessor_Macros */

/* ----------------------------------------------------------------------------
-- TSI Register Masks
---------------------------------------------------------------------------- */

/**
* @addtogroup TSI_Register_Masks TSI Register Masks
* @{
*/

/* GENCS Bit Fields */
#define TSI_GENCS_CURSW_MASK                   0x2u
#define TSI_GENCS_CURSW_SHIFT                   1
#define TSI_GENCS_EOSF_MASK                   0x4u
#define TSI_GENCS_EOSF_SHIFT                   2
#define TSI_GENCS_SCNIP_MASK                   0x8u
#define TSI_GENCS_SCNIP_SHIFT                   3
#define TSI_GENCS_STM_MASK                      0x10u
#define TSI_GENCS_STM_SHIFT                   4
#define TSI_GENCS_STPE_MASK                   0x20u
#define TSI_GENCS_STPE_SHIFT                   5
#define TSI_GENCS_TSIIEN_MASK                   0x40u
#define TSI_GENCS_TSIIEN_SHIFT                6
#define TSI_GENCS_TSIEN_MASK                   0x80u
#define TSI_GENCS_TSIEN_SHIFT                   7
#define TSI_GENCS_NSCN_MASK                   0x1F00u
#define TSI_GENCS_NSCN_SHIFT                   8
#define TSI_GENCS_NSCN(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
#define TSI_GENCS_PS_MASK                      0xE000u
#define TSI_GENCS_PS_SHIFT                      13
#define TSI_GENCS_PS(x)                         (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
#define TSI_GENCS_EXTCHRG_MASK                0x70000u
#define TSI_GENCS_EXTCHRG_SHIFT                16
#define TSI_GENCS_EXTCHRG(x)                   (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
#define TSI_GENCS_DVOLT_MASK                   0x180000u
#define TSI_GENCS_DVOLT_SHIFT                   19
#define TSI_GENCS_DVOLT(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
#define TSI_GENCS_REFCHRG_MASK                0xE00000u
#define TSI_GENCS_REFCHRG_SHIFT                21
#define TSI_GENCS_REFCHRG(x)                   (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
#define TSI_GENCS_MODE_MASK                   0xF000000u
#define TSI_GENCS_MODE_SHIFT                   24
#define TSI_GENCS_MODE(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
#define TSI_GENCS_ESOR_MASK                   0x10000000u
#define TSI_GENCS_ESOR_SHIFT                   28
#define TSI_GENCS_OUTRGF_MASK                   0x80000000u
#define TSI_GENCS_OUTRGF_SHIFT                31
/* DATA Bit Fields */
#define TSI_DATA_TSICNT_MASK                   0xFFFFu
#define TSI_DATA_TSICNT_SHIFT                   0
#define TSI_DATA_TSICNT(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
#define TSI_DATA_SWTS_MASK                      0x400000u
#define TSI_DATA_SWTS_SHIFT                   22
#define TSI_DATA_DMAEN_MASK                   0x800000u
#define TSI_DATA_DMAEN_SHIFT                   23
#define TSI_DATA_TSICH_MASK                   0xF0000000u
#define TSI_DATA_TSICH_SHIFT                   28
#define TSI_DATA_TSICH(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
/* TSHD Bit Fields */
#define TSI_TSHD_THRESL_MASK                   0xFFFFu
#define TSI_TSHD_THRESL_SHIFT                   0
#define TSI_TSHD_THRESL(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
#define TSI_TSHD_THRESH_MASK                   0xFFFF0000u
#define TSI_TSHD_THRESH_SHIFT                   16
#define TSI_TSHD_THRESH(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)

/**
* @}
*/ /* end of group TSI_Register_Masks */

/* TSI - Peripheral instance base addresses */
/** Peripheral TSI0 base pointer */
#define TSI0_BASE_PTR                         ((TSI_MemMapPtr)0x40045000u)
/** Array initializer of TSI peripheral base pointers */
#define TSI_BASE_PTRS                         { TSI0_BASE_PTR }

/* ----------------------------------------------------------------------------
-- TSI - Register accessor macros
---------------------------------------------------------------------------- */

/**
* @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros
* @{
*/

/* TSI - Register instance definitions */
/* TSI0 */
#define TSI0_GENCS                            TSI_GENCS_REG(TSI0_BASE_PTR)
#define TSI0_DATA                               TSI_DATA_REG(TSI0_BASE_PTR)
#define TSI0_TSHD                               TSI_TSHD_REG(TSI0_BASE_PTR)
接着就是各种功能的函数
void TSI_Init (void)
{
  SIM_SCGC5 |= SIM_SCGC5_TSI_MASK;  // Enable clock gating for TSI

  /* Enable proper GPIO as TSI channels */
  PORTB_PCR16 = PORT_PCR_MUX(0); // PTB16 as TSI channel 9
  PORTB_PCR17 =  PORT_PCR_MUX(0); // PTB17 as TSI channel 10
  PORTC_PCR0 =  PORT_PCR_MUX(0); // PTB17 as TSI channel 13
  NVIC_DisableIRQ((IRQn_Type)TSI0_IRQn);

  TSI0_GENCS |= (TSI_GENCS_ESOR_MASK
               | TSI_GENCS_MODE(0)
               | TSI_GENCS_REFCHRG(4)
               | TSI_GENCS_DVOLT(0)
               | TSI_GENCS_EXTCHRG(7)
               | TSI_GENCS_PS(4)
               | TSI_GENCS_NSCN(11)
               | TSI_GENCS_TSIIEN_MASK
               | TSI_GENCS_STPE_MASK
               //| TSI_GENCS_STM_MASK    //Trigger for the module 0=Sofware
               );

  TSI0_GENCS |= TSI_GENCS_TSIEN_MASK;

  TSI_SelfCalibration();
}
TSI校验标准化感觉可以去掉
void TSI_SelfCalibration(void)
{
  unsigned char cnt;
  unsigned char trigger_backup;

  TSI0_GENCS |= TSI_GENCS_EOSF_MASK;    // Clear End of Scan Flag
  TSI0_GENCS &= ~TSI_GENCS_TSIEN_MASK; // Disable TSI module

  if(TSI0_GENCS & TSI_GENCS_STM_MASK)    // Back-up TSI Trigger mode from Application
   trigger_backup = TRUE;
  else
   trigger_backup = FALSE;

  TSI0_GENCS &= ~TSI_GENCS_STM_MASK;    // Use SW trigger
  TSI0_GENCS &= ~TSI_GENCS_TSIIEN_MASK; // Enable TSI interrupts

  TSI0_GENCS |= TSI_GENCS_TSIEN_MASK;    // Enable TSI module

  for(cnt=0; cnt < total_electrode; cnt++)  // Get Counts when Electrode not pressed
  {
TSI0_DATA = ((elec_array[cnt] << TSI_DATA_TSICH_SHIFT) );
TSI0_DATA |= TSI_DATA_SWTS_MASK;
while(!(TSI0_GENCS & TSI_GENCS_EOSF_MASK));
TSI0_GENCS |= TSI_GENCS_EOSF_MASK;
gu16Baseline[cnt] = (TSI0_DATA & TSI_DATA_TSICNT_MASK);
  }

  TSI0_GENCS &= ~TSI_GENCS_TSIEN_MASK; // Disable TSI module
  TSI0_GENCS |= TSI_GENCS_TSIIEN_MASK;    // Enale TSI interrupt
  if(trigger_backup)                   // Restore trigger mode
TSI0_GENCS |= TSI_GENCS_STM_MASK;
  else
TSI0_GENCS &= ~TSI_GENCS_STM_MASK;

  TSI0_GENCS |= TSI_GENCS_TSIEN_MASK;    // Enable TSI module

TSI0_DATA = ((elec_array[0]<<TSI_DATA_TSICH_SHIFT) );
TSI0_DATA |= TSI_DATA_SWTS_MASK;

}

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