如何根据DDR_Stress_Test的结果更新flash_header.S?

guaguashao · 发表于 2015-4-4 10:52:24

各位飞思卡尔的FAE

我使用的开发板内存为海力士的h5tq4g63afr-pbc x 4，共2GB。
我参考内存的data sheet，用DDR Stress Tester得到如下结果。
我想知道如何把得到的信息反映到uboot-imx的flash_header.S中？
除了
Read DQS Gating calibration
Read calibration
Write calibration

的结果外，还有需要反映到flash_header.S中的信息吗？

----------------------------------------------
Would you like to run the write leveling calibration? (y/n)
  Please enter the MR1 value on the initilization script
  This will be re-programmed into MR1 after write leveling calibration
  Enter as a 4-digit HEX value, example 0004, then hit enter
0004 You have entered: 0x0004
Start write leveling calibration
Write leveling calibration completed
MMDC_MPWLDECTRL0 ch0 after write level cal: 0x00360039
MMDC_MPWLDECTRL1 ch0 after write level cal: 0x002D0034
MMDC_MPWLDECTRL0 ch1 after write level cal: 0x000E0017
MMDC_MPWLDECTRL1 ch1 after write level cal: 0x00110023

Would you like to run the DQS gating, read/write delay calibration? (y/n)
Starting DQS gating calibration...
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BYTE 0:
      Start:          HC=0x01 ABS=0x34
      End:          HC=0x03 ABS=0x70
      Mean:          HC=0x02 ABS=0x52
      End-0.5*tCK:    HC=0x02 ABS=0x70
      Final:          HC=0x02 ABS=0x70
BYTE 1:
      Start:          HC=0x01 ABS=0x3C
      End:          HC=0x03 ABS=0x74
      Mean:          HC=0x02 ABS=0x58
      End-0.5*tCK:    HC=0x02 ABS=0x74
      Final:          HC=0x02 ABS=0x74
BYTE 2:
      Start:          HC=0x00 ABS=0x28
      End:          HC=0x03 ABS=0x64
      Mean:          HC=0x02 ABS=0x06
      End-0.5*tCK:    HC=0x02 ABS=0x64
      Final:          HC=0x02 ABS=0x64
BYTE 3:
      Start:          HC=0x01 ABS=0x28
      End:          HC=0x03 ABS=0x64
      Mean:          HC=0x02 ABS=0x46
      End-0.5*tCK:    HC=0x02 ABS=0x64
      Final:          HC=0x02 ABS=0x64
BYTE 4:
      Start:          HC=0x00 ABS=0x1C
      End:          HC=0x03 ABS=0x5C
      Mean:          HC=0x01 ABS=0x7B
      End-0.5*tCK:    HC=0x02 ABS=0x5C
      Final:          HC=0x02 ABS=0x5C
BYTE 5:
      Start:          HC=0x01 ABS=0x10
      End:          HC=0x03 ABS=0x58
      Mean:          HC=0x02 ABS=0x34
      End-0.5*tCK:    HC=0x02 ABS=0x58
      Final:          HC=0x02 ABS=0x58
BYTE 6:
      Start:          HC=0x01 ABS=0x14
      End:          HC=0x03 ABS=0x4C
      Mean:          HC=0x02 ABS=0x30
      End-0.5*tCK:    HC=0x02 ABS=0x4C
      Final:          HC=0x02 ABS=0x4C
BYTE 7:
      Start:          HC=0x01 ABS=0x08
      End:          HC=0x03 ABS=0x40
      Mean:          HC=0x02 ABS=0x24
      End-0.5*tCK:    HC=0x02 ABS=0x40
      Final:          HC=0x02 ABS=0x40

DQS calibration MMDC0 MPDGCTRL0 = 0x02740270, MPDGCTRL1 = 0x02640264

DQS calibration MMDC1 MPDGCTRL0 = 0x0258025C, MPDGCTRL1 = 0x0240024C

Note: Array result[] holds the DRAM test result of each byte.
   0: test pass.  1: test fail
   4 bits respresent the result of 1 byte.
   result 00000001:byte 0 fail.
   result 00000011:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x11111111
ABS_OFFSET=0x08080808 result[02]=0x11111111
ABS_OFFSET=0x0C0C0C0C result[03]=0x11111111
ABS_OFFSET=0x10101010 result[04]=0x11111111
ABS_OFFSET=0x14141414 result[05]=0x11111111
ABS_OFFSET=0x18181818 result[06]=0x11111011
ABS_OFFSET=0x1C1C1C1C result[07]=0x11111011
ABS_OFFSET=0x20202020 result[08]=0x01100011
ABS_OFFSET=0x24242424 result[09]=0x00000010
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00000000
ABS_OFFSET=0x58585858 result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000
ABS_OFFSET=0x60606060 result[18]=0x00000000
ABS_OFFSET=0x64646464 result[19]=0x00000000
ABS_OFFSET=0x68686868 result[1A]=0x00000000
ABS_OFFSET=0x6C6C6C6C result[1B]=0x00000000
ABS_OFFSET=0x70707070 result[1C]=0x00001000
ABS_OFFSET=0x74747474 result[1D]=0x10111111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111

MMDC0 MPRDDLCTL = 0x46444C4A, MMDC1 MPRDDLCTL = 0x484C4A48

Starting Write calibration...

ABS_OFFSET=0x00000000 result[00]=0x11101111
ABS_OFFSET=0x04040404 result[01]=0x11101001
ABS_OFFSET=0x08080808 result[02]=0x00001000
ABS_OFFSET=0x0C0C0C0C result[03]=0x00000000
ABS_OFFSET=0x10101010 result[04]=0x00000000
ABS_OFFSET=0x14141414 result[05]=0x00000000
ABS_OFFSET=0x18181818 result[06]=0x00000000
ABS_OFFSET=0x1C1C1C1C result[07]=0x00000000
ABS_OFFSET=0x20202020 result[08]=0x00000000
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00010000
ABS_OFFSET=0x58585858 result[16]=0x00010010
ABS_OFFSET=0x5C5C5C5C result[17]=0x00010010
ABS_OFFSET=0x60606060 result[18]=0x01010010
ABS_OFFSET=0x64646464 result[19]=0x01111110
ABS_OFFSET=0x68686868 result[1A]=0x11111110
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11111111
ABS_OFFSET=0x70707070 result[1C]=0x11111111
ABS_OFFSET=0x74747474 result[1D]=0x11111111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111

MMDC0 MPWRDLCTL = 0x36322C38,MMDC1 MPWRDLCTL = 0x36323428

MMDC registers updated from calibration

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x02740270
MPDGCTRL1 PHY0 (0x021b0840) = 0x02640264
MPDGCTRL0 PHY1 (0x021b483c) = 0x0258025C
MPDGCTRL1 PHY1 (0x021b4840) = 0x0240024C

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x46444C4A
MPRDDLCTL PHY1 (0x021b4848) = 0x484C4A48

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x36322C38
MPWRDLCTL PHY1 (0x021b4850) = 0x36323428

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