KL26Z-SPI通信

spromise · 发表于 2015-7-21 16:06:11

本帖最后由 spromise 于 2015-7-21 16:28 编辑

因为正在做KL26Z的SPI通信，现在需要通过DMA实现SPI的读写，求助一个可以用的DMA实现SPI的通信的例程，最好是作为SPI从机实现的，希望各路大侠相助，万分感谢！！！！！

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lkl0305 · 发表于 2015-7-21 20:49:58

官方库中有啊

FSL_TICS_ZP · 发表于 2015-7-22 08:08:55

例程代码分享，你可以参考一下

复制代码

void spi0_dma_master_spi1_slave(void)
{
unsigned char k=0;
unsigned char dummy = 0;
unsigned char sendData = 0;
unsigned char readData = 0;
SIM_SCGC6 |= SIM_SCGC6_DMACHMUX_MASK; //DMAMUX Clock Gate Control: 1, clock enable---
SIM_SCGC7 |= SIM_SCGC7_DMA_MASK; //DMA Clock Gate control: 1, clock enable----
m_tdata8[0] = 0xF0;
m_tdata8[1] = 0x11;
m_tdata8[2] = 0x22;
m_tdata8[3] = 0x33;
m_tdata8[4] = 0x44;
m_tdata8[5] = 0x66;
m_tdata8[6] = 0x77;
m_tdata8[7] = 0x88;
for (k=0; k<8; k++)
m_rdata8[k] = 0;
s_tdata8[0] = 0x01;
s_tdata8[1] = 0x23;
s_tdata8[2] = 0x45;
s_tdata8[3] = 0x67;
s_tdata8[4] = 0x89;
s_tdata8[5] = 0xAB;
s_tdata8[6] = 0xCD;
s_tdata8[7] = 0xEF;
for (k=0; k<8; k++)
s_rdata8[k] = 0;
dma_int_cnt = 0; //this variable is used to indicates the count of transmission interrupt
extend_cnt = 0;
enable_irq(0); //DMA channel 0 transfer complete and error interrupt
enable_irq(1); //DMA channel 1 transfer complete and error interrupt
enable_irq(2); //DMA channel 2 transfer complete and error interrupt
enable_irq(3); //DMA channel 3 transfer complete and error interrupt
/* SIM_CLKDIV1 = ( 0
| SIM_CLKDIV_OUTDIV(0x1)
| SIM_CLKDIV_OUTDIV(0) ); // what usage?*/
//
//SPI0 receive dma source number is 16; SPI0 transmint dma source number is 17
//*****channel 0--->TX, channel 1----->RX************
DMAMUX0_CHCFG(0) |= DMAMUX_CHCFG_ENBL_MASK & (~DMAMUX_CHCFG_TRIG_MASK);
DMAMUX0_CHCFG(0) |= DMAMUX_CHCFG_SOURCE(17); //TX---DMA channel 0-SPI0 source number--ENBL=1--TRIG=0---
DMAMUX0_CHCFG(1) |= DMAMUX_CHCFG_ENBL_MASK & (~DMAMUX_CHCFG_TRIG_MASK);
DMAMUX0_CHCFG(1) |= DMAMUX_CHCFG_SOURCE(16); //RX---DMA channel 1-SPI0 source number--ENBL=1--TRIG=0---
//*****channel 2--->TX, channel 3----->RX************
DMAMUX0_CHCFG(2) |= DMAMUX_CHCFG_ENBL_MASK & (~DMAMUX_CHCFG_TRIG_MASK);
DMAMUX0_CHCFG(2) |= DMAMUX_CHCFG_SOURCE(19); //TX---DMA channel 2-SPI1 source number--ENBL=1--TRIG=0---
DMAMUX0_CHCFG(3) |= DMAMUX_CHCFG_ENBL_MASK & (~DMAMUX_CHCFG_TRIG_MASK);
DMAMUX0_CHCFG(3) |= DMAMUX_CHCFG_SOURCE(18); //RX---DMA channel 3-SPI1 source number--ENBL=1--TRIG=0---
//************channel request number ???????*****************
DMA_SAR0 = (uint32_t)(&(m_tdata8));
DMA_DAR0 = (uint32_t)(&(SPI0_DL));
// DMA_SAR0 = (uint32_t)(&(SPI0_D));
// DMA_DAR0 = (uint32_t)(&(m_rdata8));
DMA_DSR_BCR0 |= DMA_DSR_BCR_BCR(8); //BCR contains the number of bytes yet to be transferred for a given block
DMA_DCR0 = DMA_DCR_ERQ_MASK|DMA_DCR_EINT_MASK|DMA_DCR_D_REQ_MASK|DMA_DCR_CS_MASK
|DMA_DCR_DSIZE(1)|DMA_DCR_SSIZE(1)|DMA_DCR_SINC_MASK; //|DMA_DCR_CS_MASK
DMA_SAR1 = (uint32_t)(&(SPI0_DL));
DMA_DAR1 = (uint32_t)(&(m_rdata8));
// DMA_SAR1 = (uint32_t)(&(m_tdata8));
// DMA_DAR1 = (uint32_t)(&(SPI0_D));
DMA_DSR_BCR1 |= DMA_DSR_BCR_BCR(8); //BCR contains the number of bytes yet to be transferred for a given block
DMA_DCR1 = DMA_DCR_ERQ_MASK|DMA_DCR_EINT_MASK|DMA_DCR_D_REQ_MASK|DMA_DCR_CS_MASK
|DMA_DCR_DSIZE(1)|DMA_DCR_SSIZE(1)|DMA_DCR_DINC_MASK; //|DMA_DCR_CS_MASK
DMA_SAR2 = (uint32_t)(&(s_tdata8)); //----tx-----
DMA_DAR2 = (uint32_t)(&(SPI1_DL));
// DMA_SAR2 = (uint32_t)(&(SPI1_D)); //----rx-----
// DMA_DAR2 = (uint32_t)(&(s_rdata8));
DMA_DSR_BCR2 |= DMA_DSR_BCR_BCR(8); //BCR contains the number of bytes yet to be transferred for a given block
DMA_DCR2 = DMA_DCR_ERQ_MASK|DMA_DCR_EINT_MASK|DMA_DCR_D_REQ_MASK|DMA_DCR_CS_MASK
|DMA_DCR_DSIZE(1)|DMA_DCR_SSIZE(1)|DMA_DCR_SINC_MASK; //|DMA_DCR_CS_MASK
DMA_SAR3 = (uint32_t)(&(SPI1_DL)); //----rx-----
DMA_DAR3 = (uint32_t)(&(s_rdata8));
// DMA_SAR3 = (uint32_t)(&(s_tdata8)); //----tx-----
// DMA_DAR3 = (uint32_t)(&(SPI1_D));
DMA_DSR_BCR3 |= DMA_DSR_BCR_BCR(8); //BCR contains the number of bytes yet to be transferred for a given block
DMA_DCR3 = DMA_DCR_ERQ_MASK|DMA_DCR_EINT_MASK|DMA_DCR_D_REQ_MASK|DMA_DCR_CS_MASK
|DMA_DCR_DSIZE(1)|DMA_DCR_SSIZE(1)|DMA_DCR_DINC_MASK; //|DMA_DCR_CS_MASK
SPI0_C1 |= SPI_C1_SSOE_MASK; //|SPI0_C1_CPOL_MASK|SPI0_C1_LSBFE_MASK;
SPI0_C2 |= SPI_C2_MODFEN_MASK;
SPI0_C1 |= SPI_C1_CPHA_MASK;
//SPI0_C1 &= (~SPI_C1_CPHA_MASK);
SPI0_C1 |= SPI_C1_CPOL_MASK;
//SPI0_C1 &= (~SPI_C1_CPOL_MASK);
//SPI0_C1 |= SPI0_C1_LSBFE_MASK;
SPI0_C1 &= (~SPI_C1_LSBFE_MASK);
//SPI0_C1 &= (~SPI0_C1_SPIE_MASK); //Disable RX interrrupt
//SPI0_C1 |= SPI0_C1_SPIE_MASK; //enable RX interrrupt
//SPI0_C1 &= (~SPI0_C1_SPTIE_MASK); //Disable the transmit interrupt
//SPI0_C1 |= SPI0_C1_SPTIE_MASK; //Enable the transime interrupt
SPI1_C1 |= SPI_C1_MSTR_MASK;
SPI1_BR = 0x02;
//SPI1_C1 &= (~SPI1_C1_MSTR_MASK); //---slave----bus clock is 12.5Mhz--0.08us--
//SPI0_BR = 0x43; //SPPR = 4, SPR = 3, bps div = (SPPR+1)*2^(SPR+1) = 80,----Tspi--6.4us
//SPI0_BR = 0x40; //bps div = 10,---------0.8us
//SPI0_BR = 0x30; //bps div = 8,----------0.64us
//SPI0_BR = 0x10; //bps div = 4,----------0.32us
//SPI0_BR = 0x00; //bps div = 2,----------0.16us----6.125Mhz
//SPI0_BR = 0x54; //bps div = 192,----------15.36us
//SPI0_BR = 0x77; //bps div = 2048,----------163.84us
// SPI1_BR = 0x01;
SPI1_C1 |= SPI_C1_SSOE_MASK;
SPI1_C2 |= SPI_C2_MODFEN_MASK;
SPI1_C1 |= SPI_C1_CPHA_MASK;
//SPI1_C1 &= (~SPI_C1_CPHA_MASK);
SPI1_C1 |= SPI_C1_CPOL_MASK;
//SPI1_C1 &= (~SPI_C1_CPOL_MASK);
//SPI1_C1 |= SPI1_C1_LSBFE_MASK;
SPI1_C1 &= (~SPI_C1_LSBFE_MASK);
SPI1_C2 |= SPI_C2_RXDMAE_MASK;
SPI0_C2 |= SPI_C2_TXDMAE_MASK;
SPI0_C2 |= SPI_C2_RXDMAE_MASK;
SPI1_C2 |= SPI_C2_TXDMAE_MASK;
SPI0_C1 |= SPI_C1_SPE_MASK;
SPI1_C1 |= SPI_C1_SPE_MASK;
// SPI0_C1 |= SPI0_C1_SPE_MASK;
for(k=0; k<8 ; k++)
{
if(s_rdata8[k] != (uint8)m_tdata8[k])
{
printf("k = 0x%01x\r\n",k);
printf("m_tdata8 = 0x%02x\r\n",(unsigned char)(m_tdata8[k] & 0xff));
printf("s_rdata8 = 0x%02x\r\n",s_rdata8[k]);
// error_count++;
printf("Transmit unsuccessful\n");
}
else
{
printf("m_tdata8 = 0x%02x\r\n",m_tdata8[k]);
printf("s_rdata8 = 0x%02x\r\n",s_rdata8[k]);
printf("Transmit successful\n");
}
if(m_rdata8[k] != (uint8)s_tdata8[k])
{
printf("k = 0x%08x\r\n",k);
printf("s_tdata8 = 0x%04x\r\n",s_tdata8[k]);
printf("m_rdata8 = 0x%04x\r\n",m_rdata8[k]);
// // error_count++;
printf("Transmit unsuccessful\n");
}
else
{
printf("s_tdata8 = 0x%04x\r\n",s_tdata8[k]);
printf("m_rdata8 = 0x%04x\r\n",m_rdata8[k]);
printf("Transmit successful\n");
}
}
while(1);
}

复制代码

spromise · 发表于 2015-7-22 09:37:40

lkl0305 发表于 2015-7-21 20:49
官方库中有啊

我有问我这边的代理他们说这个型号的例程没有哦

spromise · 发表于 2015-7-22 09:38:27

FSL_TICS_ZP 发表于 2015-7-22 08:08

谢谢大侠我去实验一下代码

lkl0305 · 发表于 2015-7-22 12:06:09

spromise 发表于 2015-7-22 09:37
我有问我这边的代理他们说这个型号的例程没有哦

都差不多吧

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