每天解决一个问题35：谈K60时钟（3）

suoma · 发表于 2015-9-27 16:58:09

本帖最后由 suoma 于 2015-9-27 16:59 编辑

先祝大家中秋快乐
接上一篇：每天解决一个问题34：谈K60时钟（2） - 飞思卡尔江湖 - 飞思卡尔技术社区 https://www.nxpic.org.cn/modul ... 1&extra=#pid2153171

时钟如何由FEI模式进入PEE模式？怎么转换呢？参考如下程序

1. unsigned char pll_init(unsigned char clk_option, unsigned char crystal_val)
2. {
3. unsigned char pll_freq;
4.
5. if (clk_option > 3) {return 0;} //return 0 if one of the available options is not selected
6. if (crystal_val > 15) {return 1;} // return 1 if one of the available crystal options is not available
7. //This assumes that the MCG is in default FEI mode out of reset.
8.
9. // First move to FBE mode
10. #if (defined(K60_CLK) || defined(ASB817))
11. MCG_C2 = 0;
12. #else
13. // Enable external oscillator, RANGE=2, HGO=1, EREFS=1, LP=0, IRCS=0
14. MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;
15. #endif
16.
17. // after initialization of oscillator release latched state of oscillator and GPIO
18. SIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;
19. LLWU_CS |= LLWU_CS_ACKISO_MASK;
20.
21. // Select external oscilator and Reference Divider and clear IREFS to start ext osc
22. // CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
23. MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
24.
25. /* if we aren't using an osc input we don't need to wait for the osc to init */
26. #if (!defined(K60_CLK) && !defined(ASB817))
27. while (!(MCG_S & MCG_S_OSCINIT_MASK)){}; // wait for oscillator to initialize
28. #endif
29.
30. while (MCG_S & MCG_S_IREFST_MASK){}; // wait for Reference clock Status bit to clear
31.
32. while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // Wait for clock status bits to show clock source is ext ref clk
33.
34. // Now in FBE
35.
36. #if (defined(K60_CLK))
37. //MCG_C5 = MCG_C5_PRDIV(0x18);
38. MCG_C5 = MCG_C5_PRDIV(0x18); //基频2M 外部时钟源是50M时, 50/25=2M
39. #else
40. // Configure PLL Ref Divider, PLLCLKEN=0, PLLSTEN=0, PRDIV=5
41. // The crystal frequency is used to select the PRDIV value. Only even frequency crystals are supported
42. // that will produce a 2MHz reference clock to the PLL.
43. MCG_C5 = MCG_C5_PRDIV(crystal_val); // Set PLL ref divider to match the crystal used
44. #endif
45.
46. // Ensure MCG_C6 is at the reset default of 0. LOLIE disabled, PLL disabled, clk monitor disabled, PLL VCO divider is clear
47. MCG_C6 = 0x0;
48. // Select the PLL VCO divider and system clock dividers depending on clocking option
49. switch (clk_option) {
50. case 0:
51. // Set system options dividers
52. //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
53. set_sys_dividers(0,0,0,1);
54. // Set the VCO divider and enable the PLL for 50MHz, LOLIE=0, PLLS=1, CME=0, VDIV=1
55. MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(1); //VDIV = 1 (x25)
56. pll_freq = 50;
57. break;
58. case 1:
59. // Set system options dividers
60. //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
61. set_sys_dividers(0,1,1,3);
62. // Set the VCO divider and enable the PLL for 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
63. MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(26); //VDIV = 26 (x50)
64. pll_freq = 100;
65. break;
66. case 2:
67. // Set system options dividers
68. //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
69. set_sys_dividers(0,1,1,3);
70. // Set the VCO divider and enable the PLL for 96MHz, LOLIE=0, PLLS=1, CME=0, VDIV=24
71. MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(24); //VDIV = 24 (x48)
72. pll_freq = 96;
73. break;
74. case 3:
75. // Set system options dividers
76. //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
77. set_sys_dividers(0,0,0,1);
78. // Set the VCO divider and enable the PLL for 48MHz, LOLIE=0, PLLS=1, CME=0, VDIV=0
79. MCG_C6 = MCG_C6_PLLS_MASK; //VDIV = 0 (x24)
80. pll_freq = 48;
81. break;
82. }
83. while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
84.
85. while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
86.
87. // Now running PBE Mode
88.
89. // Transition into PEE by setting CLKS to 0
90. // CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
91. MCG_C1 &= ~MCG_C1_CLKS_MASK;
92.
93. // Wait for clock status bits to update
94. while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};
95.
96. // Now running PEE Mode
97.
98. return pll_freq;
99. } //pll_init

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JackieLaura · 发表于 2015-9-28 11:15:28

代码比较多，对于英文比较差的加点中文注释就更好理解了

suoma · 发表于 2015-9-28 20:53:30

JackieLaura 发表于 2015-9-28 11:15
代码比较多，对于英文比较差的加点中文注释就更好理解了

后面都有英文注释

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