KL46的PIT定时中断熟悉底层代码的大神请进

nick950222 · 发表于 2015-11-13 10:36:20

在做智能车的测试题，相用两个定时器pit0和pit1，这样的话稳定一点。但是两个定时器用的是一个中断向量，所以需要在中断函数里判断中断标志，有没有大神知道如何判断呢？小弟新手上路，跪求大神帮忙。

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FSL_TICS_ZP · 发表于 2015-11-13 10:41:23

在KL46中，PIT0与PIT1都有对应的PIT_TFLGn寄存器，TIF就是它们所对应的中断标志。

hisstone · 发表于 2015-11-13 11:51:15

楼主可参考示例：\KSDK_1.3.0\examples\frdmkl46z\driver_examples\pit中fsl_pit_irq.c

#include <stdlib.h>
#include <assert.h>
#include "fsl_pit_driver.h"
#include "fsl_clock_manager.h"
/*******************************************************************************
* Variables
******************************************************************************/
extern volatile bool pitIsrFlag[2];
/*******************************************************************************
* Code
******************************************************************************/
/*!
* @brief System default IRQ handler defined in startup code.
*/
#if FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER
#if defined(KM34Z7_SERIES)
void PIT0_PIT1_IRQHandler(void)
{
uint32_t i;
for(i=0; i < PIT_INSTANCE_COUNT; i++)
{
if (CLOCK_SYS_GetPitGateCmd(i))
{
for(i=0; i < FSL_FEATURE_PIT_TIMER_COUNT; i++)
{
if (PIT_HAL_IsIntPending(g_pitBase[0], i))
{
/* Clear interrupt flag.*/
PIT_HAL_ClearIntFlag(g_pitBase[0], i);
pitIsrFlag[i] = true;
}
}
}
}
}
#else
void PIT_IRQHandler(void)
{
uint32_t i;
for(i=0; i < 2; i++) // We only support two channels for pit example
{
if (PIT_HAL_IsIntPending(g_pitBase[0], i))
{
/* Clear interrupt flag.*/
PIT_HAL_ClearIntFlag(g_pitBase[0], i);
pitIsrFlag[i] = true;
}
}
}
#endif
#else
#if (FSL_FEATURE_PIT_TIMER_COUNT > 0U)
void PIT0_IRQHandler(void)
{
/* Clear interrupt flag.*/
PIT_HAL_ClearIntFlag(g_pitBase[0], 0U);
pitIsrFlag[0] = true;
}
#endif
#if (FSL_FEATURE_PIT_TIMER_COUNT > 1U)
void PIT1_IRQHandler(void)
{
/* Clear interrupt flag.*/
PIT_HAL_ClearIntFlag(g_pitBase[0], 1U);
pitIsrFlag[1] = true;
}
#endif
#endif /* FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER */
/*! @} */

复制代码

hisstone · 发表于 2015-11-13 11:55:09

相关结构定义：

/** PIT - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
uint8_t RESERVED_0[220];
__I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
__I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
uint8_t RESERVED_1[24];
struct { /* offset: 0x100, array step: 0x10 */
__IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
__I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
__IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
} CHANNEL[2];
} PIT_Type, *PIT_MemMapPtr;
#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
/*!
* @brief Reads the current timer timeout flag.
*
* Every time the timer counts to 0, this flag is set.
*
* @param base Base address for current PIT instance.
* @param channel Timer channel number
* @return Current status of the timeout flag
* - true: Timeout has occurred.
* - false: Timeout has not yet occurred.
*/
static inline bool PIT_HAL_IsIntPending(PIT_Type * base, uint32_t channel)
{
assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
return PIT_RD_TFLG(base, channel);
}