mpc8548 nand flash读写问题求助

johncetc

各位好，有谁熟悉MPC8548 的nand flash,
我遇到如下问题，
读数据从基地址有时读出的是最后一次发出的命令，即0x30读停止命令，
写数据很少成功，发现时序时好时坏，代码使用的就是官网推荐使用的基本程序，
哪位大神遇到过类似问题，可能什么原因，是硬件还是软件，
难道是MPC8548 的 MDR寄存器写入ram array，还需要再读一下才能正确写入么
for(i=0; i<64;i++)
{
*(int *)0x40005088 = UPMATable[i];
*(char*)(0xf0000000)=0x0;
}
没头绪，nand flash好用么，为什么这么不稳定，

我知道答案 目前已有7人回答

阅读全文

anger0925

检查一下硬件时序问题

FQYD01

帮顶一下               

FSL_TICS_lunmin

"代码使用的就是官网推荐使用的基本程序"，请问是什么程序？

johncetc

anger0925 发表于 2015-11-26 08:51
检查一下硬件时序问题

的确是程序跑着跑着时序就乱了，UPMATable数组对应的时序配置输入MDR寄存器，然后通过命令触发芯片的控制器发出对应的时序，反复检查过，现在读、写、读ID，擦除功能都能执行，只是有时时序不对就会出错，即使出错后重复执行也可能不成功，纠结啊

johncetc

FSL_TICS_lunmin 发表于 2015-11-26 14:58
"代码使用的就是官网推荐使用的基本程序"，请问是什么程序？

官网上的例子，nand_init,run_pattern,nand_read,nand_write,nand_read_id之类的简单C程序

FSL_TICS_lunmin

你好，这里确实有点问题。

关于Program Ram Array和MAD 请参考下面的描述和给出的示例步骤：

Patterns are written to the RAM array by setting MxMR[OP] = 01 and accessing the UPM with any write
transaction that hits the relevant chip select. The entire array is thus programmed by an alternating series
of writes: to MDR (RAM word to be written) each time followed by a read from MDR and then followed
by a (dummy) write transaction to the relevant UPM assigned bank. A read from MDR is required to
ensure that the MDR update has occurred prior to the (dummy) write transaction.
RAM array contents may also be read for debug purposes, for example, by alternating dummy read
transactions, each time followed by reads of MDR (when MxMR[OP] = 10).

UPM Programming Example (Two Sequential Writes to the RAM Array)
The following example further illustrates the steps required to perform two writes to the RAM array at
non-sequential addresses assuming that the relevant BRn and ORn registers have been previously setup.
1. Program MxMR for the first write (with desired RAM array address).
2. Write pattern/data to MDR to ensure that the MxMR has already been updated with the desired
configuration.
3. Read MDR to ensure that the MDR has already been updated with the desired pattern. (Or, read
MxMR if step 2 is not performed.)
4. Preform a dummy write transaction. (Write transaction can now be performed.)
5. Read/check MxMR[MAD]. If incremented, then the previous dummy write transaction is
completed; proceed to step 6. Repeat step 5 until incremented.
6. Program MxMR for the second write with the desired RAM array address.
7. Write pattern/data to MDR to ensure that the MxMR has already been updated with the desired
configuration.
8. Read MDR to ensure that the MDR has already been updated with the desired pattern.
9. Perform a dummy write transaction.(Write transaction can now be performed.)
10. Read/check MxMR[MAD]. If incremented, then the previous dummy write transaction is
completed.
Note that if step 1 (or 6) and 2 (or 7) are reversed, then step 3 (or 8) is replaced by the following:
• Read MxMR to ensure that the MxMR has already been updated with the desired configuration.

UPM Programming Example (Two Sequential Reads from the RAM Array)
RAM array contents may also be read for debug purposes, for example, by alternating dummy read
transactions, each time followed by reads of MDR (when MxMR[OP] = 0b10). The following example
further illustrates the steps required to perform two reads from the RAM array at non-sequential addresses
assuming that the relevant BRn and ORn registers have been previously setup.
1. Program MxMR for the first read with the desired RAM array address.
2. Read MxMR to ensure that the MxMR has already been updated with the desired configuration,
such as RAM array address.
3. Perform a dummy read transaction.(Read transaction can now be performed.)
4. Read/check MxMR[MAD]. If incremented, then the previous dummy read transaction is
completed; proceed to step 5. Repeat step 4 until incremented.
5. Read MDR.
6. Program MxMR for the second read with the desired RAM array address.
7. Read MxMR to ensure that the MxMR has already been updated with the desired configuration,
such as RAM array address.
8. Perform a dummy read transaction.(Read transaction can now be performed.)
Local Bus Controller
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor 13-63
9. Read/check MxMR[MAD]. If incremented, then the previous dummy read transaction is
completed; proceed to step 10. Repeat step 9 until incremented.
10. Read MDR.

johncetc

FSL_TICS_lunmin 发表于 2015-11-26 16:40
你好，这里确实有点问题。

关于Program Ram Array和MAD 请参考下面的描述和给出的示例步骤：

非常感谢，我先对照着再调试看看，有问题再来请教