版主,我在起kernel的时候发现arch/arm/mach-imx/clk-imx6q.c中:
writel_relaxed(1 << CCM_CCGR_OFFSET(0), base + 0x7c);重新设置了DDR寄存器,会导致lpddr2挂了,串口没有输出。
想问一下为什么这里还要设置一次,看代码解释:
/*
* These two clocks (mmdc_ch0_axi and mmdc_ch1_axi) were incorrectly
* implemented as gate at the beginning. To fix them with the minimized
* impact, let's point them to their dividers.
*/