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- 2016-5-24
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有没有大神,帮我解释一下下面的KL25低功耗例程中的代码,最好详细点,初学者。万分感谢!int main (void)
{
#ifdef CMSIS
start();
#endif
/*Enable all operation modes because this is a write once register*/
SMC_PMPROT = SMC_PMPROT_AVLLS_MASK |
SMC_PMPROT_ALLS_MASK |
SMC_PMPROT_AVLP_MASK;
/*PTC3(SW3) is configured to wake up MCU from VLLSx and LLS modes, Interrup is ne*/
LLWU_Init();
/*Configure Tower hardware for the application*/
Port_Init(IO_NMI_DEF);
SW_LED_Init();
EnableInterrupts;
/*Start test*/
LowPowerModes_test();
}
void LowPowerModes_test(void)
{
int i;
unsigned char op_mode,fcrdiv_val;
int test_num = UNDEF_VALUE;
int wait_count;
char test_val;
while(1)
{
while (test_num > 22 | test_num < 0){
LED0_ON;
LED1_ON;
LED2_ON;
#ifndef FREEDOM
LED3_ON;
#endif
if ((SMC_PMSTAT & SMC_PMSTAT_PMSTAT_MASK)== 4){
printf(" in VLPR Mode ! ");
} else if ((SMC_PMSTAT & SMC_PMSTAT_PMSTAT_MASK)== 1){
printf(" in Run Mode ! ");
}
printf("\n\r > ");
test_val = uart0_getchar(UART0_BASE_PTR);
uart0_putchar(UART0_BASE_PTR,test_val);
printf("\n\r");
if((test_val>=0x30) && (test_val<=0x39))
test_num = test_val - 0x30;
if((test_val>=0x41) && (test_val<=0x4C))
test_num = test_val - 0x37;
if((test_val>=0x61) && (test_val<=0x6C))
test_num = test_val - 0x57;
}
LED0_OFF;
LED1_OFF;
LED2_OFF;
#ifndef FREEDOM
LED3_OFF;
case 3://LLS loop wake up every 1000 ms
printf("Press any key to enter LLS with LPTMR 1 Second wakeup loop\n\r ");
uart0_getchar(UART0_BASE_PTR);
llwu_configure(0x0000, LLWU_PIN_FALLING, 0x1);
LPTMR_init(1000,LPTMR_USE_LPOCLK);
printf("Press SW4 to wake up from VLLS2\n\r ");
for (i=0;i<10;i++)
{
printf(" Entering LLS mode");
clockMonitor(OFF);
set_4_lp(0);
enter_lls();
set_4_lp(1);
clockMonitor(ON);
/*After LLS wake up that was enter from PEE the exit will be on PBE */
/* for this reason after wake up make sure to get back to desired */
/* clock mode */
op_mode = what_mcg_mode();
if(op_mode==PBE)
{
mcg_clk_hz = pbe_pee(CLK0_FREQ_HZ);
uart0_clk_khz = ((mcg_clk_hz / 2) / 1000); // UART0 clock frequency will equal half the PLL frequency
uart_configure(uart0_clk_khz,SIM_SOPT2_UART0SRC(1));
}
printf(" Loop Count 0x%02X ",i) ;
printf(" Back in RUN mode \n\r");
}
LPTMR0_CSR &= ~LPTMR_CSR_TEN_MASK;
break;
case 0x12://VLPR in BLPI 4 MHZ
/*Maximum clock frequency for this mode is core 4MHz and Flash 1Mhz*/
printf("Press any key to enter VLPR in BLPI mode \n\r ");
uart0_getchar(UART0_BASE_PTR);
printf("Configure clock frequency to 4MHz core clock and 1MHz flash clock\n\r ");
/*Get out of VLPR to change clock dividers*/
exit_vlpr(); // get out of VLPR back to RUN
vlp_clock_config(BLPI);
// default clock divider is set to divide by 1 of Fast IRC and Div2 for Bus
SIM_CLKDIV1 = ( SIM_CLKDIV1_OUTDIV1(0)
| SIM_CLKDIV1_OUTDIV4(4) );
fcrdiv_val = (1 << ((MCG_SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); // calculate the fast IRC divder factor
mcg_clk_hz = (fast_irc_freq / fcrdiv_val); // MCGOUT frequency equals fast IRC frequency divided by 2
mcg_clk_hz = mcg_clk_hz / (((SIM_CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> 28)+ 1);
/*Go to VLPR*/
enter_vlpr(); // get into VLPR
if ((SMC_PMSTAT & SMC_PMSTAT_PMSTAT_MASK)== 4){
printf(" in VLPR Mode !\n\r ");
} else if ((SMC_PMSTAT & SMC_PMSTAT_PMSTAT_MASK)== 1){
printf(" in Run Mode !\n\r ");
clockMonitor(ON);
}
break;
void demo_lptmr_isr(void)
{
volatile unsigned int dummyread;
if(MCM_CPO & MCM_CPO_CPOACK_MASK){
MCM_CPO &= ~MCM_CPO_CPOREQ_MASK;
while (MCM_CPO & MCM_CPO_CPOACK_MASK);
printf(" \n\rLPTRM Interrupt pulled OUT of Compute Mode \n\r");
}
SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK;
printf(" \r[demo_lptmr_isr] \n\r > ");
LPTMR0_CSR |= LPTMR_CSR_TCF_MASK; // write 1 to TCF to clear the LPT timer compare flag
LPTMR0_CSR = ( LPTMR_CSR_TEN_MASK | LPTMR_CSR_TIE_MASK | LPTMR_CSR_TCF_MASK );
// enable timer
// enable interrupts
// clear the flag
/*wait for write to complete to before returning */
dummyread = LPTMR0_CSR;
return;
void SW_LED_Init(void)
{
#ifdef TOWER
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTA_MASK ; /* PORT clock enablement */
LED0_EN; // (PORTA_PCR16 = PORT_PCR_MUX(1))
GPIOA_PDDR |= (1<<16);
LED1_EN; // (PORTA_PCR17 = PORT_PCR_MUX(1))
GPIOA_PDDR |= (1<<17);
LED2_EN; // (PORTB_PCR8 = PORT_PCR_MUX(1))
GPIOB_PDDR |= (1<<8);
LED3_EN; // (PORTA_PCR5 = PORT_PCR_MUX(1))
GPIOA_PDDR |= (1<<5);
#else
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTD_MASK ; /* PORT clock enablement */
LED0_EN;
GPIOB_PDDR |= (1<<19);
LED1_EN;
GPIOB_PDDR |= (1<<18);
LED2_EN;
GPIOD_PDDR |= 1;
#endif
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