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本帖最后由 andrewz 于 2016-11-29 09:56 编辑
Configure the I2C bit rate:
• Divide the system clock (I2C_PCLK) by a factor of 2. See Table 211 “I2C Clock Divider
register (CLKDIV, address 0x4005 0014 (I2C0), 0x4005 4014 (I2C1), 0x4007 0014
(I2C2), 0x4007 4014 (I2C3)) bit description”.
• Set the SCL high and low times to 2 clock cycles each. This is the default. See
Table 214 “Master Time register (MSTTIME, address 0x4005 0024 (I2C0), 0x4005
4024 (I2C1), 0x4007 0024 (I2C2), 0x4007 4024 (I2C3)) bit description”. The result is
an SCL clock of 375 kHz.
这里30M的时钟 /2 /4 = 3.75M.
不知道上面是怎么求到的375KHz.
感觉RM似乎写得很仔细.但是用起来,谁用谁知道啊~
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