DDR 校准

amwha · 发表于 2016-12-5 16:08:40

硬件配置:
i.mx6D ,DDR 为镁光的MT41K128M16JT-125K,两片，只用了一个片选 CS0.

I.MX6DQSDL DDR3 Script Aid V0.10.XLSX的配置如下：

Device Information
Manufacturer:	Micron
Memory part number:	MT41K128M16JT-125K
Memory type:	DDR3-1600
DRAM density (Gb)	2
DRAM Bus Width	16
Number of Banks	8
Number of ROW Addresses	14
Number of COLUMN Addresses	10
Page Size (K)	2
Self-Refresh Temperature (SRT)	Normal
tRCD=tRP=CL (ns)	13.75
tRC Min (ns)	48.75
tRAS Min (ns)	35
System Information
i.Mx Part	i.Mx6D
Bus Width	32
Density per chip select (Gb)	4
Number of Chip Selects used	1
Total DRAM Density (Gb)	4
DRAM Clock Freq (MHz)	528
DRAM Clock Cycle Time (ns)	1.894
Address Mirror (for CS1)	Disable
SI Configuration
DRAM DSE Setting - DQ/DQM (ohm)	48
DRAM DSE Setting - ADDR/CMD/CTL (ohm)	48
DRAM DSE Setting - CK (ohm)	48
DRAM DSE Setting - DQS (ohm)	48
System ODT Setting (ohm)	60

Q1:以上配置不知道为没有问题?

然后把inc文件拷贝出来，把里面的看门狗去掉
//=============================================================================
//init script for i.Mx6D DDR3
//=============================================================================
// Revision History
// v01
//=============================================================================

wait = on
//=============================================================================
// Disable WDOG
//=============================================================================
//setmem /16 0x020bc000 = 0x30

//=============================================================================
// Enable all clocks (they are disabled by ROM code)
//=============================================================================
setmem /32 0x020c4068 = 0xffffffff
setmem /32 0x020c406c = 0xffffffff
setmem /32 0x020c4070 = 0xffffffff
setmem /32 0x020c4074 = 0xffffffff
setmem /32 0x020c4078 = 0xffffffff
setmem /32 0x020c407c = 0xffffffff
setmem /32 0x020c4080 = 0xffffffff
setmem /32 0x020c4084 = 0xffffffff

//=============================================================================
// IOMUX
//=============================================================================
//DDR IO TYPE:
setmem /32 0x020e0798 = 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
setmem /32 0x020e0758 = 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE

//CLOCK:
setmem /32 0x020e0588 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
setmem /32 0x020e0594 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1

//ADDRESS:
setmem /32 0x020e056c = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
setmem /32 0x020e0578 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
setmem /32 0x020e074c = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_ADDDS

//Control:
setmem /32 0x020e057c = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
setmem /32 0x020e058c = 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
setmem /32 0x020e059c = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
setmem /32 0x020e05a0 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
setmem /32 0x020e078c = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_CTLDS

//Data Strobes:
setmem /32 0x020e0750 = 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
setmem /32 0x020e05a8 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
setmem /32 0x020e05b0 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
setmem /32 0x020e0524 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
setmem /32 0x020e051c = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
//setmem /32 0x020e0518 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
//setmem /32 0x020e050c = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
//setmem /32 0x020e05b8 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
//setmem /32 0x020e05c0 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7

//Data:
setmem /32 0x020e0774 = 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
setmem /32 0x020e0784 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B0DS
setmem /32 0x020e0788 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B1DS
setmem /32 0x020e0794 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B2DS
setmem /32 0x020e079c = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B3DS
//setmem /32 0x020e07a0 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B4DS
//setmem /32 0x020e07a4 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B5DS
//setmem /32 0x020e07a8 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B6DS
//setmem /32 0x020e0748 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B7DS

setmem /32 0x020e05ac = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
setmem /32 0x020e05b4 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
setmem /32 0x020e0528 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
setmem /32 0x020e0520 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
//setmem /32 0x020e0514 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
//setmem /32 0x020e0510 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
//setmem /32 0x020e05bc = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
//setmem /32 0x020e05c4 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7

//=============================================================================
// DDR Controller Registers
//=============================================================================
// Manufacturer: Micron
// Device Part Number: MT41K128M16JT-125
// Clock Freq.: 528MHz
// Density per CS in Gb: 4
// Chip Selects used: 1
// Number of Banks: 8
// Row address: 14
// Column address: 10
// Data bus width 32
//=============================================================================
setmem /32 0x021b001c = 0x00008000 MMDC0_MDSCR, set the Configuration request bit during MMDC set up

//=============================================================================
// Calibration setup.
//=============================================================================
setmem /32 0x021b0800 = 0xA1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

// For target board, may need to run write leveling calibration to fine tune these settings.
setmem /32 0x021b080c  = 0x0017001A
setmem /32 0x021b0810 = 0x00210011
//setmem /32 0x021b480c  = 0x00000000
//setmem /32 0x021b4810 = 0x00000000

////Read DQS Gating calibration
setmem /32 0x021b083c = 0x03440350 // MPDGCTRL0 PHY0
setmem /32 0x021b0840 = 0x03400348 // MPDGCTRL1 PHY0
//setmem /32 0x021b483c = 0x00000000 // MPDGCTRL0 PHY1
//setmem /32 0x021b4840 = 0x00000000 // MPDGCTRL1 PHY1

//Read calibration
setmem /32 0x021b0848 = 0x3A303838 // MPRDDLCTL PHY0
//setmem /32 0x021b4848 = 0x40404040 // MPRDDLCTL PHY1

//Write calibration
setmem /32 0x021b0850 = 0x3C3A4038 // MPWRDLCTL PHY0
//setmem /32 0x021b4850 = 0x40404040 // MPWRDLCTL PHY1

//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)
setmem /32 0x021b081c = 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3
setmem /32 0x021b0820 = 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3
setmem /32 0x021b0824 = 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3
setmem /32 0x021b0828 = 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3
//setmem /32 0x021b481c = 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3
//setmem /32 0x021b4820 = 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3
//setmem /32 0x021b4824 = 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3
//setmem /32 0x021b4828 = 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3

//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented
//setmem /32 0x021b08c0 = 0x24911492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
//setmem /32 0x021b48c0 = 0x24911492

// Complete calibration by forced measurement:
setmem /32 0x021b08b8 = 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
//setmem /32 0x021b48b8 = 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
//=============================================================================
// Calibration setup end
//=============================================================================

//MMDC init:
setmem /32 0x021b0004 = 0x00020036 // MMDC0_MDPDC
setmem /32 0x021b0008 = 0x09444040 // MMDC0_MDOTC
setmem /32 0x021b000c = 0x54597955 // MMDC0_MDCFG0
setmem /32 0x021b0010 = 0xFF328F64 // MMDC0_MDCFG1
setmem /32 0x021b0014 = 0x01FF00DB // MMDC0_MDCFG2

//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC
setmem /32 0x021b001c = 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up
setmem /32 0x021b002c = 0x000026D2 // MMDC0_MDRWD
setmem /32 0x021b0030 = 0x00591023 // MMDC0_MDOR
setmem /32 0x021b0040 = 0x00000017 // Chan0 CS0_END
setmem /32 0x021b0000 = 0x83190000 // MMDC0_MDCTL

//Mode register writes
setmem /32 0x021b001c = 0x02088032 // MMDC0_MDSCR, MR2 write, CS0
setmem /32 0x021b001c = 0x00008033 // MMDC0_MDSCR, MR3 write, CS0
setmem /32 0x021b001c = 0x00048031 // MMDC0_MDSCR, MR1 write, CS0
setmem /32 0x021b001c = 0x19408030 // MMDC0_MDSCR, MR0write, CS0
setmem /32 0x021b001c = 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0

//setmem /32 0x021b001c = 0x0208803A // MMDC0_MDSCR, MR2 write, CS1
//setmem /32 0x021b001c = 0x0000803B // MMDC0_MDSCR, MR3 write, CS1
//setmem /32 0x021b001c = 0x00048039 // MMDC0_MDSCR, MR1 write, CS1
//setmem /32 0x021b001c = 0x19408038 // MMDC0_MDSCR, MR0write, CS1
//setmem /32 0x021b001c = 0x04008048 // MMDC0_MDSCR, ZQ calibration command sent to device on CS1

setmem /32 0x021b0020 = 0x00007800 // MMDC0_MDREF

setmem /32 0x021b0818 = 0x00022227 // DDR_PHY_P0_MPODTCTRL
//setmem /32 0x021b4818 = 0x00022227 // DDR_PHY_P1_MPODTCTRL

setmem /32 0x021b0004 = 0x00025576 // MMDC0_MDPDC now SDCTL power down enabled

setmem /32 0x021b0404 = 0x00011006 // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.

setmem /32 0x021b001c = 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)

开始进行压力测试：
1、选 800MHZ 的主频率    -> 1
2、选 512MB的内存             ->2
3、选校准频率528MHZ       ->y
4、选MR1的值                   ->0004

我做了三块板（2#，4#，5#），其中一块做了两次，得到了校准参数：

2#
MMDC_MPWLDECTRL0 CH0 0X0015001A
MMDC_MPWLDECTRL1 CH0 0X001A000B
MPDGCTRL0 PHY0    = OX0340034C
MPDGCTRL0 PHY0    = OX03340338
MPRDDLCTL  PHY0 =  0X3E34383C
MPWRDLCTL  PHY0 =  0X38383C3A

4#0
MMDC_MPWLDECTRL0 CH0 0X00140019
MMDC_MPWLDECTRL1 CH0 0X00160009
MPDGCTRL0 PHY0    = OX03400344
MPDGCTRL0 PHY0    = OX0334033C
MPRDDLCTL  PHY0 =  0X42344040
MPWRDLCTL  PHY0 =  0X3E3A403C

4#1
MMDC_MPWLDECTRL0 CH0 0X0014001B
MMDC_MPWLDECTRL1 CH0 0X0019000C
MPDGCTRL0 PHY0    = 0X03400344
MPDGCTRL0 PHY0    = 0X0334033C
MPRDDLCTL  PHY0 =  0X42344040
MPWRDLCTL  PHY0 =  0X3E3A403C

5#
MMDC_MPWLDECTRL0 CH0 0X0011001B
MMDC_MPWLDECTRL1 CH0 0X00160009
MPDGCTRL0 PHY0    = 0X03400348
MPDGCTRL0 PHY0    = 0X0334033C
MPRDDLCTL  PHY0 =  0X3E30363A
MPWRDLCTL  PHY0 =  0X3C384036

Q2:同一批次的板子得到的参数不一样，而且同一板子测试两次得到的参数也不一样，这是为什么啊？我们如何得到合适的校准参数啊？

得到的六个值回写到 inc文件里进行压力测试，测试了一天多，没有问题。

Q3: inc里的值是不是只要把标红的更新到flash_header.s里？还是说要对一遍所有的，以.inc里的为准，更新到flash_header.s?

我知道答案目前已有9人回答

阅读全文

小智MM · 发表于 2016-12-5 17:11:03

本帖最后由小智MM 于 2016-12-5 17:12 编辑

楼主你好，关于Q2回答如下：
这个现象并不奇怪，说明DDR在布线上有一些问题，造成了在某个频率上出现临界点，这个临界点附近是不稳定的，有时候可以跑过去，有时候跑不过去。但是，如果在528MHz，400MHz时，每次都可以通过，并且是稳定的，就可以配置为528MHz或者400MHz。

小智MM · 发表于 2016-12-5 17:11:23

每次做DDR压力测试，528MHz总是可以通过，那么就配置为528MHz，这是我们标准，并且MMDC支持的时钟频率。

小智MM · 发表于 2016-12-5 17:11:53

这个DDR test不是用来校准的，是测试DDR工作性能的。你这里使用528M就是OK的。

小智MM · 发表于 2016-12-5 17:13:56

关于另外两个问题，关于DDR的设置，建议你参考你芯片的手册和参数来设置。你可以参考一下我们论坛中的帖子：
https://www.nxpic.org.cn/module/forum/thread-594371-1-1.html
https://www.nxpic.org.cn/module/forum/thread-606303-1-1.html

amwha · 发表于 2016-12-5 17:15:10

小智MM 发表于 2016-12-5 17:11
这个DDR test不是用来校准的，是测试DDR工作性能的。你这里使用528M就是OK的。 ...

你好，Q3,我应该怎么做？

jackten · 发表于 2016-12-5 17:32:37

谢谢分享

lkl0305 · 发表于 2016-12-5 21:02:28

学习一下

huixin · 发表于 2016-12-6 09:20:00

真不懂

baxk1986 · 发表于 2016-12-7 09:57:54

学习一下....

[求助] DDR 校准

浏览过的版块

站长推荐 /3