[LPC1768]时钟树的配置

jobszheng5

[LPC1768]时钟树的配置

    我们的微处理器都有一个叫主频的东西，也代表着微处理器的处理能力。早在51单片机的时代曾经喊出来1T的概念，即微处理器的主频与处理能力能够持平。进入Cortex-M时代后，随着指令集的不断进步，微处理器的处理能力大增，部分微处理器的处理能力已经可以超过主频速度，在此不做举例了。我们回到本次试用的主角LPC1768上来，其最高主频可达100MHz，也带来了强大的处理能力。本次实验就是配置LPC1768的时钟。
    LPC1768有三个时钟输入时钟源，分别为外部晶振，内部晶振与低频时钟源，其框架图如下图所示：

    上图引自LPC1768的用词手册，从框图也可以看出，我们需要配置时钟源多路选择器，Main PLL（PLL0）等多个模块，涉及到以下多个寄存器：

CLKSRCSEL Clock Source Select Register

Phase Locked Loop (PLL0, Main PLL)

PLL0CON PLL0 Control Register

PLL0CFG PLL0 Configuration Register

PLL1CFG PLL1 Configuration Register

CCLKCFG CPU Clock Configuration Register

PCONP Power Control for Peripherals Register

    我们本次并未使用时钟频率输出，因此CLKOUTCFG Clock Output Configuration Register寄存器并未配置使用。

    时钟的配置需要稳定与可靠，所以配置的流程也相当重要，我们按照官方手册来设计配置流程：

The following sequence must be followed step by step in order to have PLL0 initialized

and running:

1. Disconnect PLL0 with one feed sequence if PLL0 is already connected.

2. Disable PLL0 with one feed sequence.

3. Change the CPU Clock Divider setting to speed up operation without PLL0, if desired.

4. Write to the Clock Source Selection Control register to change the clock source if

needed.

5. Write to the PLL0CFG and make it effective with one feed sequence. The PLL0CFG

can only be updated when PLL0 is disabled.

6. Enable PLL0 with one feed sequence.

7. Change the CPU Clock Divider setting for the operation with PLL0. It is critical to do

this before connecting PLL0.

8. Wait for PLL0 to achieve lock by monitoring the PLOCK0 bit in the PLL0STAT register,

or using the PLOCK0 interrupt, or wait for a fixed time when the input clock to PLL0 is

slow (i.e. 32 kHz). The value of PLOCK0 may not be stable when the PLL reference

frequency (FREF, the frequency of REFCLK, which is equal to the PLL input

frequency divided by the pre-divider value) is less than 100 kHz or greater than

20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time

has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF

seconds when FREF is less than 400 kHz.

9. Connect PLL0 with one feed sequence.

    时钟配置完成之后，我们使用systick的计时中断，并通过IAR调试环境的实时刷新数据来粗略估计配置的正确性。代码如下：

1. void main(void)
   
2. {
   
3.   uint8_t i = 0;  
   
4.   setXtalToMax();  
   
5.   SysTick_Config(100000);  
   
6.   while(1)
   
7.   {
   
8.     i++;   
   
9.   }  
   
10. }
    
11. void SysTick_Handler(void)
    
12. {
    
13.   gCnt++;
    
14. }

复制代码

    其实，我们应该使用时钟的分频输出功能，将时钟主频输出并使用示波器来测量。好吧，就偷个懒吧！

    TO BE CONTINUED.

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XDLH

这款没有性价比了，已经推了很多年了！

jobszheng5

XDLH 发表于 2019-2-19 14:41
这款没有性价比了，已经推了很多年了！

现在NXP把freescale买下后，我觉得原来的飞思卡尔的产品线也不推了，原来的LPC系列的也不推了。