MPC5644A烧写程序前需要下载的内存初始化文件如何配置

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// MULTI Server Script
// Freescale MPC564x demo board setup script for MPServ


// Whether or not to check for VLE
eval $vle_check = 1

target t 0 rst

// Determine chip family (A, L, etc.)
eval $tmp_midr2 = *((volatile unsigned int*)0xc3f90008);
eval $tmp_family = (($tmp_midr2 >> 8) & 0xff);



if ($tmp_family == 'L') {
    // MPC564xL

    // Determine LSM/DPM
    eval $tmp_sscm_status = *((volatile unsigned int*)0xc3fd8000);
    if ($tmp_sscm_status & 0x80000000) {
        eval $leopard_lsm = 1
    } else {
        eval $leopard_dpm = 1
    }
}
if ($tmp_family == 0) {
    // MPC564xA midr2 is at SIU_BASE+0x0
    eval $tmp_midr2 = *((volatile unsigned int*)0xc3f90000);
    eval $tmp_family = (($tmp_midr2 >> 8) & 0xff);
    if ($tmp_family == 0) {
        // other
        print "Unrecognized target type. Defaulting to 564xA."
        $tmp_family = 'A'
    }
}


if ($tmp_family == 'L') {
    // Clear functional and destructive reset status.
    memwrite 4 0xc3fe4000 0xffffffff

    // Check FCCU for critical faults. A SWT critical fault can result from
    // the probe resetting the target if the probe is unable to disable the
    // SWT before the timeout occurs.
    memwrite 4 0xffe6c000 0x3 // Read FCCU_STAT
    eval $tmp_fccu_stat = *((volatile unsigned int*)0xffe6c0c0);
    if ($tmp_fccu_stat == 0x3) {
        print "FCCU fault detected"
        memwrite 4 0xffe6c000 0x9 // Read FCCU_CFS
        eval $tmp_fccu_cfs = *((volatile unsigned int*)0xffe6c06c);
        if ($tmp_fccu_cfs & 0x4000) {
            print "FCCU SWT critical fault detected. Attempting to correct..."
            memwrite 4 0xffe6c07c 0x618b7a50 // FCCU_CFK
            memwrite 4 0xffe6c06c 0x00004000 // FCCU_CFS0
        }
    }
    // Check once more for critical faults
    memwrite 4 0xffe6c000 0x9 // Read FCCU_CFS
    eval $tmp_fccu_cfs = *((volatile unsigned int*)0xffe6c06c);
    if ($tmp_fccu_cfs) {
        mprintf("Unable to correct all critical faults. CFS=0x%08x\n", $tmp_fccu_cfs)
    } else {
        print "FCCU shows no faults."

        // Now try to move into drun mode
        memwrite 4 0xc3fdc00c 0x0000001f // ME_IS
        memwrite 4 0xc3fdc02c 0x001f0010 // ME_DRUN_MC
        memwrite 4 0xc3fdc004 0x30005af0 // ME_MCTL
        memwrite 4 0xc3fdc004 0x3000a50f // ME_MCTL
        wait -time 100
    }

    if ($leopard_dpm) {
        // Bring up the second core
        memwrite 4 0x50000100 0x48000000 // write a spin opcode
        memwrite 4 0xc3fd8018 0x50000100 // DPMBOOT
        memwrite 4 0xc3fd801c 0x5af0     // DPMKEY
        memwrite 4 0xc3fd801c 0xa50f     // DPMKEY
        target t 1 th
        // Clear the default tlb mapping
        target t 1 tlbw 0 0 0 0 0
    }
}


target t * rw msr 0x02000000


// Initialize vector pointers to internal SRAM
target t * rw ivpr 0x40000000
target t * rw ivor0 0x0010
target t * rw ivor1 0x0020
target t * rw ivor2 0x0030
target t * rw ivor3 0x0040
target t * rw ivor4 0x0050
target t * rw ivor5 0x0060
target t * rw ivor6 0x0070
target t * rw ivor7 0x0080
target t * rw ivor8 0x0090
target t * rw ivor9 0x00a0
target t * rw ivor10 0x00b0
target t * rw ivor11 0x00c0
target t * rw ivor12 0x00d0
target t * rw ivor13 0x00e0
target t * rw ivor14 0x00f0
target t * rw ivor15 0x0100
target t * rw ivor32 0x0110
target t * rw ivor33 0x0120
target t * rw ivor34 0x0130



if ($tmp_family == 'A') {                 // MPC564xA
    // set PMC_TRIMR[V33TRIM] = 0b1000 per MPC5644A EVB rework guide
    memwrite 4 0xc3fbc004 0x00008000
}

if ($tmp_family != 'A') {
    // 564xA doesn't have MC_ME

    // Enable access to peripheral registers
    // ME_RUN_PC0 = 0xfe
    memwrite 4 0xc3fdc080 0xfe
}

// Setup the TLB to map the Peripheral Bridge A
// Set the Guard (G) flag because this entry points to I/O registers.
target t * tlbw 5 0xc3f00000 v,size=0xa,i,g,ux,sx,uw,sw,ur,sr 0xc3f00000 iprot

// Check for VLE.
// If the .vletext exists, we will assume that the entire program is built in
// VLE mode. If different/additional pages need to have VLE enabled, this is
// where to do it.
if ($vle_check == 1 && ($M_sec_exists(".vletext") || $PROGRAMMING_FLASH))  {

    // Turn on VLE bit for internal SRAM
    target t * tlbw 3 0x40000000 vle,v,size=0x8,ux,sx,uw,sw,ur,sr 0x40000000 iprot
    if ($leopard_dpm) {
        target t * tlbw 4 0x50000000 vle,v,size=0x8,ux,sx,uw,sw,ur,sr 0x50000000 iprot
    }

    // Turn on VLE bit for flash
    target t * tlbw 1 0x00000000 vle,v,size=0xe,ux,sx,uw,sw,ur,sr 0x00000000 iprot

    // Fill exception vectors with VLE branch-to-self
    target mf 0x40000000 0x200 0xe800e800
    $RAM_VLE = 1;
} else {
    // Normal PPC ISA
    // Setup the TLB to map the internal SRAM
    target t * tlbw 3 0x40000000 v,size=0x8,ux,sx,uw,sw,ur,sr 0x40000000 iprot
    if ($leopard_dpm) {
        target t * tlbw 4 0x50000000 v,size=0x8,ux,sx,uw,sw,ur,sr 0x50000000 iprot
    }

    // Setup the TLB to map 16MB of flash space
    target t * tlbw 1 0x00000000 v,size=0xe,ux,sx,uw,sw,ur,sr 0x00000000 iprot   

    // Fill exception vectors with branch-to-self
    target mf 0x40000000 0x200 0x48000000
}


// Enable the L1 instruction cache
eval $tmp_midr = *(0xc3f90004)
if ((($tmp_midr >> 16) == 0x5640) || ($tmp_midr2 == 0)) { // rev 1.0
    //pass
} else {
    target t * rw l1csr1 0x103
    target t * rw l1csr1 0x1
}

if ($tmp_family == 'L') {         // MPC564xL
    if ($leopard_lsm) {
        // On the MPC564xL in lock step mode, it is necessary to initialize the
        // GPRs and the ACC register so that the values match on both cores.
        eval $i = 0;
        while ($i < 32) {
                substitute target rw r%EVAL{mprintf("%d", $i)} 0x0
                eval $i = $i+1
        }
        target rw acc 0x0
    }

    // Make sure pins used by trace are enabled
    memwrite 2 0xc3f90118 0x4800    // MDO[8]
    memwrite 2 0xc3f9011a 0x4800    // MDO[9]
    memwrite 2 0xc3f9011c 0x4800    // MDO[10]
    memwrite 2 0xc3f9011e 0x4800    // MDO[11]

    memwrite 2 0xc3f90120 0x4800    // MDO[7]
    memwrite 2 0xc3f90122 0x4800    // MDO[6]
    memwrite 2 0xc3f90124 0x4800    // MDO[5]
    memwrite 2 0xc3f90126 0x4800    // MDO[4]


    memwrite 2 0xc3f900e8 0x4800    // MDO[3]
    memwrite 2 0xc3f900ea 0x4800    // MDO[2]
    memwrite 2 0xc3f900ec 0x4800    // MDO[1]
    memwrite 2 0xc3f900ee 0x4800    // MCKO
    memwrite 2 0xc3f900f0 0x4800    // MSEO[1]
    memwrite 2 0xc3f900f2 0x4800    // MSEO[0]
    memwrite 2 0xc3f900f4 0x4800    // EVTO
}


substitute if (%EVAL{__tracearchid} == 11) {

    // These options must be set manually in MULTI 5
    if (_MULTI_MAJOR_VERSION > 5) {
        trace set "Trace Clock Multiplier" "1/1x"
        if ($tmp_family == 'A') {
            // Andorra claims to support 12-bit MDO, but we have only seen
            // 4-bit work so far
            trace set "MDO Data Port Width" "4 bits"
        }
        if (($tmp_family == 'L') && (($tmp_midr & 0x7c00) != 0x4000)) {
            // Some MPC564xL packages only support 4-bit MDO.
            trace set "MDO Data Port Width" "4 bits"
        }
    }



    if (($tmp_family == 'L') && ($leopard_lsm == 1) && (($tmp_midr & 0xff) == 0)) {         // MPC564xL
        // LSM - stalling is not supported with cut1 chips.
        trace set overflow_avoidance_method none
    } else {
        trace set overflow_avoidance_method stall
    }

}

eval $tmp_midr = *((volatile unsigned int*)0xc3f90004);
eval $tmp_sf = (($tmp_midr2 >> 31) & 0x1);
eval $tmp_partnum = (($tmp_midr >> 16) & 0xffff);

if (($tmp_family == 'A' || $tmp_family == 'L') && $tmp_sf == 1 && $tmp_partnum == 0x5640 && $PROGRAMMING_FLASH) { // SPC564A70, SPC56EL70
    // Clear primary low/mid lock bits
    memwrite 4 0xc3f88004 0xA1A11111
    memwrite 4 0xc3f88004 0x80100000
    // Clear high lock bits
    memwrite 4 0xc3f88008 0xB2B22222
    memwrite 4 0xc3f88008 0x80000000
    // Clear secondary low/mid lock bits
    memwrite 4 0xc3f8800c 0xC3C33333
    memwrite 4 0xc3f8800c 0x80100000
}

if ($tmp_family == 'S' && $PROGRAMMING_FLASH) {         // MPC564xS
    // more peripherals
    target t * tlbw 6 0xffe00000 v,size=0xd,i,g,sr,sw,sx 0xffe00000 iprot //2MB
    // more peripherals
    target t * tlbw 7 0x90000000 v,size=0xd,i,g,sr,sw,sx 0x90000000 iprot //2MB
    // QuadSPI A
    memwrite 2 0xc3f900e6 0x70c // IO0
    memwrite 2 0xc3f900e8 0x70c // IO1
    memwrite 2 0xc3f900e2 0x70c // IO2
    memwrite 2 0xc3f900e4 0x70c // IO3
    memwrite 2 0xc3f900e0 0x70f // CS
    memwrite 2 0xc3f900ea 0x600 // SCLK
    // QuadSPI A
    memwrite 2 0xc3f900d8 0x70c // IO0
    memwrite 2 0xc3f900d6 0x70c // IO1
    memwrite 2 0xc3f90134 0x70c // IO2
    memwrite 2 0xc3f90130 0x70c // IO3
    memwrite 2 0xc3f9012c 0x70f // CS
    memwrite 2 0xc3f9012e 0x600 // SCLK
    // QuadSPI clocks
    memwrite 4 0xc3fe0398 0 // CGM_AC1_SC.SELCTL
    eval $tmp_cgm_ac3_dc0 = *((volatile unsigned int*)0xc3fe039c);
    memwrite 4 0xc3fe039c 0x80000000 // CGM_AC1_DC0.DIV0
    // Spansion external flash
    memwrite 4 0xfffa0000 0x000f0010 // QSPI_MCR
}

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