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[其他] clrc663如何设置寄存器读取14443B卡的UID

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2021-10-18
发表于 2019-12-10 16:53:54 | 显示全部楼层 |阅读模式
大家好!我们现在想要用clrc663读取14443B卡的UID,在网上也找到了驱动代码 RC663_ISO14443B_ReqB.jcf
代码如下:我们现在是用LPC11E68X串口驱动clrc663,请问如何通过串口来设置clrc663 ,并读取 14443B卡的UID.

CLL
CHB 115200
//> Load Protocol
SR  0F 98 //        Timer0 Timer starts at the end of transmission
SR 37 FF
SR  14 92 //Timer1 Timer starts at the end of transmission
SR  19 20 //Timer2
SR  1A 03 //TReload Hi
SR  1B FF //TReload Lo
SR  1E 00 //Timer3
SR  02 90 //FIFO control register ->sets FIFO size to 255bytes
SR  03 FE //Waterlevel settings
SR  0C 80 //RXBitCtrl (Values AfterColl)
SR  28 8F //DrvMode_Reg both driver pins enable, invert one driver
SR  29 CC //00  TXAmp_Reg: set continous wave amplitude, set residual carrier
SR  2A 01 //DrvCon_Reg: sets driver config to TXEnvelope
SR  2B 05 //Txl_Reg: sets iiLoad, was auch immer das ist
SR  34 00 //RxSofD_Reg: Subcarrier and SOF detection off
SR  38 12 //Rcv_Reg: defines input for signal processing and defines collision level

SR  00 00 //Idle commmand

SR  02 B0 //FIFO Control

SR  06 7F //IRQ0_Reg:
SR  07 7F //IRQ1_Reg:
SR  05 04 // write Tx and RX protocol numbers (04 for ISO14443B)
SR  05 04 // write Tx and RX protocol numbers (04 for ISO14443B)
SR  08 10 //IRQ0En_Reg: IdleIrq is enable propagated to GlobalIRQ
SR  09 40 //IRQ1En_Reg: GlobalIrq propagated to the interrupt pin
SR  00 0D //LoadProtocol


SR  08 00 //Reset IRQ0
SR  09 00 //Reset IRQ1
SR  02 B0 //FIFO Control
// Init registers.
SR  2C 7B
SR  2D 7B
SR  2E 08
SR  2F 0A //00
SR  30 00
SR  31 01
SR  33 05 // 05
SR  34 B2
SR  35 34
SR  37 3F //CC
SR  38 12
SR  39 0A //00
// End of load protocol




//> ==============================================
//> Field Reset
//> ==============================================

// Field off: Read out DrvMod register. Disable Drivers
GR  28    // Response:  87
SR  28 87




//> phhalHw_FieldOn
SR  28 8F
SLP 100


//> Send REQB command

SR 31 C1
SR 32 0B
SR 00 00
SR 02 B0
SR 06 7F
SR 07 7F

SR  05 05 // Response:  05
SR 05 00
SR 05 00
SR  00 07 // Response:  00

SLP 100
//> Read ATQB from FIFO
RE 04 0C    // Read FIFOLevel (12 bytes)
RE 05 50    // ATQB 1st byte
GR 05       // ATQB PUPI
GR 05       // ATQB PUPI
GR 05       // ATQB PUPI
GR 05       // ATQB PUPI
GR 05       // ATQB Application data
GR 05       // ATQB Application data
GR 05       // ATQB Application data
GR 05       // ATQB Application data
GR 05       // ATQB Protocol Info
GR 05       // ATQB Protocol Info
GR 05       // ATQB Protocol Info
GR 05       // ATQB Protocol Info

GR 05       // ATQB Protocol Info
GR 05       // ATQB Protocol Info
GR 05       // ATQB Protocol Info
GR 05       // ATQB Protocol Info
GR 05       // ATQB Protocol Info
GR 05       // ATQB Protocol Info

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