imx6ull+DDR3L，系统能正常跑通，压力测试不过

yhlpp

imx6ull+DDR3L，系统能正常跑通，压力测试不过。

测试软件版本：ddr_stress_tester_v3.00
测试配置文件版本：I.MX6ULL_DDR3_Script_Aid_V0.01.xlsx    和    I.MX6UL_DDR3_Script_Aid_V0.02.xlsx 都试过。

进行DDR校准的时候报错如下：  

============================================
        DDR Stress Test (3.0.0)
        Build: Dec 14 2018, 14:13:23
        NXP Semiconductors.
============================================

============================================
        Chip ID
CHIP ID = i.MX6 UltraLiteLite(0x65)
Internal Revision = TO1.1
============================================

============================================
        Boot Configuration
SRC_SBMR1(0x020d8004) = 0x10004961
SRC_SBMR2(0x020d801c) = 0x01000001
============================================

ARM Clock set to 528MHz

============================================
        DDR configuration
DDR type is DDR3
Data width: 16, bank num: 8
Row size: 14, col size: 10
Chip select CSD0 is used
Density per chip select: 256MB
============================================

Current Temperature: 38
============================================

DDR Freq: 396 MHz

ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
  MPWLHWERR register read out for factory diagnostics:
  MPWLHWERR PHY0 = 0x00000000


HW WL cal status: no suitable delay value found for byte 0

HW WL cal status: no suitable delay value found for byte 1
Write leveling calibration completed but failed, the following results were found:
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F
Write DQS delay result:
   Write DQS0 delay: 31/256 CK
   Write DQS1 delay: 31/256 CK


Error: failed during write leveling calibration



希望各位专家不吝赐教

我知道答案 目前已有3人回答

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yhlpp

顶上去

小智MM

压力测试跑不过，应该还是一些参数设置的不合理，需要做调整。

eefocus_3945441

楼主解决了吗，我也是这个问题