怎么给imx6d降低ddr3频率

xqt123

各位大神好：

imx型号为imx6d7cvt，ddr3型号为skhynix h5TQ2G63FFR pbc，一共四块，总共1G,由于系统长期运行不太稳定，想测试是否由于ddr频率造成的，需要对其降频。

我使用ddr-test-uboot-jtag-mx6dq.bin进行测试，在不调整电压参数情况下，用400Mhz，直接失败，如下
MX6Q SABRESD U-Boot > go 0x00907000
## Starting application at 0x00907000 ...

============================================
        DDR Stress Test (3.0.0)
        Build: Dec 14 2018, 14:20:05
        NXP Semiconductors.
============================================

============================================
        Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.2
============================================

============================================
        Boot Configuration
SRC_SBMR1(0x020d8004) = 0x01001860
SRC_SBMR2(0x020d801c) = 0x22000001
============================================

What ARM core speed would you like to run?
Type 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz  
ARM Clock set to 800MHz

============================================
        DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 14, col size: 10
Chip select CSD0 is used
Density per chip select: 1024MB
============================================

Current Temperature: 47
============================================

Please select the DDR density per chip select (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MB  
For maximum supported density (4GB), we can only access up to 3.75GB.  Type 7 to select this
  DDR density selected (MB): 256


Would do you want to change VDD_SOC_CAP/VDD_ARM_CAP voltage? Type 'y' to run and 'n' to skip


Would do you want run DDR Calibration? Type 'y' to run and 'n' to skip


The DDR stress test can run with an incrementing frequency or at a static freq
To run at a static freq, simply set the start freq and end freq to the same value
Would do you want run DDR Stress Test? Type 'y' to run and 'n' to skip

Enter desired START freq (135 to 672 MHz), then hit enter.
Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.
400
  The freq you entered was: 400

Enter desired END freq (135 to 672 MHz), then hit enter.
Make sure this is equal to or greater than start freq
600
  The freq you entered was: 600

Do you want to run DDR Stress Test for simple loop or Over Night Test?
Type '0' for simple loop. Type '1' for Over Night Test

DDR Stress Test Iteration 1
Current Temperature: 47
============================================

DDR Freq: 396 MHz
t0.1: data is addr test
Address of failure(step2): 0x10000044
Data was: 0x1000004c
But pattern  should match address
Error: failed to run stress test!!!



调整电压参数之后（随便勾选的），可以校准成功，如下


Please select the DDR density per chip select (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MB  
For maximum supported density (4GB), we can only access up to 3.75GB.  Type 7 to select this
  DDR density selected (MB): 256


Would do you want to change VDD_SOC_CAP/VDD_ARM_CAP voltage? Type 'y' to run and 'n' to skip

Please select VDD_SOC_CAP volatage on the board
Type 0 for 1.15V; 1 for 1.175V; 2 for 1.2V; 3 for 1.225V; 4 for 1.25V; 5 for 1.275V; 6 for 1.3V  
VDD_SOC_CAP option: 4

Please select VDD_ARM_CAP volatage on the board
Type 0 for 1.15V; 1 for 1.175V; 2 for 1.2V; 3 for 1.225V; 4 for 1.25V; 5 for 1.275V; 6 for 1.3V  
  VDD_ARM_CAP option: 4


Would do you want run DDR Calibration? Type 'y' to run and 'n' to skip

Calibration will run at DDR frequency 528MHz. Type 'y' to continue.
If you want to run at other DDR frequency. Type 'n'
Enter the DDR frequency for calibration [350MHz to 528MHz]:  
420
  The freq you entered was: 420
  Please enter the MR1 value on the initilization script
  This will be re-programmed into MR1 after write leveling calibration
  Enter as a 4-digit HEX value, example 0004, then hit enter
0004DDR Freq: 413 MHz

ddr_mr1=0x00000004
Start write leveling calibration...
running Write level HW calibration
  MPWLHWERR register read out for factory diagnostics:
  MPWLHWERR PHY0 = 0x3e3e3e3e
  MPWLHWERR PHY1 = 0x3e3e3e3e

Write leveling calibration completed, update the following registers in your initialization script
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00150015
    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001A0017
    MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x0014001F
    MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x000D001A
Write DQS delay result:
   Write DQS0 delay: 21/256 CK
   Write DQS1 delay: 21/256 CK
   Write DQS2 delay: 23/256 CK
   Write DQS3 delay: 26/256 CK
   Write DQS4 delay: 31/256 CK
   Write DQS5 delay: 20/256 CK
   Write DQS6 delay: 26/256 CK
   Write DQS7 delay: 13/256 CK

Starting DQS gating calibration
. HC_DEL=0x00000000        result[00]=0x11111111
. HC_DEL=0x00000001        result[01]=0x10011111
. HC_DEL=0x00000002        result[02]=0x00000000
. HC_DEL=0x00000003        result[03]=0x11111111
. HC_DEL=0x00000004        result[04]=0x11111111
. HC_DEL=0x00000005        result[05]=0x11111111
. HC_DEL=0x00000006        result[06]=0x11111111
. HC_DEL=0x00000007        result[07]=0x11111111
. HC_DEL=0x00000008        result[08]=0x11111111
. HC_DEL=0x00000009        result[09]=0x11111111
. HC_DEL=0x0000000A        result[0A]=0x11111111
. HC_DEL=0x0000000B        result[0B]=0x11111111
. HC_DEL=0x0000000C        result[0C]=0x11111111
. HC_DEL=0x0000000D        result[0D]=0x11111111
DQS HC delay value low1 = 0x02020202, high1=0x02020202
DQS HC delay value low2 = 0x02010102, high2=0x02020202

loop ABS offset to get HW_DG_LOW
. ABS_OFFSET=0x00000000        result[00]=0x11111111
...
. ABS_OFFSET=0x0000007C        result[1F]=0x11111111

loop ABS offset to get HW_DG_HIGH
. ABS_OFFSET=0x00000000        result[00]=0x11111111
...
. ABS_OFFSET=0x0000007C        result[1F]=0x11111111


BYTE 0:
        Start:                 HC=0x01 ABS=0x48
        End:                 HC=0x02 ABS=0x3C
        Mean:                 HC=0x02 ABS=0x02
        End-0.5*tCK:         HC=0x01 ABS=0x3C
        Final:                 HC=0x02 ABS=0x02
BYTE 1:
        Start:                 HC=0x01 ABS=0x48
        End:                 HC=0x02 ABS=0x3C
        Mean:                 HC=0x02 ABS=0x02
        End-0.5*tCK:         HC=0x01 ABS=0x3C
        Final:                 HC=0x02 ABS=0x02
BYTE 2:
        Start:                 HC=0x01 ABS=0x48
        End:                 HC=0x02 ABS=0x3C
        Mean:                 HC=0x02 ABS=0x02
        End-0.5*tCK:         HC=0x01 ABS=0x3C
        Final:                 HC=0x02 ABS=0x02
BYTE 3:
        Start:                 HC=0x01 ABS=0x48
        End:                 HC=0x02 ABS=0x3C
        Mean:                 HC=0x02 ABS=0x02
        End-0.5*tCK:         HC=0x01 ABS=0x3C
        Final:                 HC=0x02 ABS=0x02
BYTE 4:
        Start:                 HC=0x01 ABS=0x48
        End:                 HC=0x02 ABS=0x3C
        Mean:                 HC=0x02 ABS=0x02
        End-0.5*tCK:         HC=0x01 ABS=0x3C
        Final:                 HC=0x02 ABS=0x02
BYTE 5:
        Start:                 HC=0x00 ABS=0x48
        End:                 HC=0x02 ABS=0x3C
        Mean:                 HC=0x01 ABS=0x42
        End-0.5*tCK:         HC=0x01 ABS=0x3C
        Final:                 HC=0x01 ABS=0x42
BYTE 6:
        Start:                 HC=0x01 ABS=0x00
        End:                 HC=0x02 ABS=0x3C
        Mean:                 HC=0x01 ABS=0x5D
        End-0.5*tCK:         HC=0x01 ABS=0x3C
        Final:                 HC=0x01 ABS=0x5D
BYTE 7:
        Start:                 HC=0x01 ABS=0x48
        End:                 HC=0x02 ABS=0x3C
        Mean:                 HC=0x02 ABS=0x02
        End-0.5*tCK:         HC=0x01 ABS=0x3C
        Final:                 HC=0x02 ABS=0x02

DQS calibration MMDC0 MPDGCTRL0 = 0x02020202, MPDGCTRL1 = 0x02020202

DQS calibration MMDC1 MPDGCTRL0 = 0x01420202, MPDGCTRL1 = 0x0202015D

Note: Array result[] holds the DRAM test result of each byte.  
      0: test pass.  1: test fail  
      4 bits respresent the result of 1 byte.   
      result 00000001:byte 0 fail.
      result 00000011:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000        result[00]=0x11111111
...
ABS_OFFSET=0x7C7C7C7C        result[1F]=0x11111111

Byte 0: (0x14 - 0x60), middle value:0x3a
Byte 1: (0x10 - 0x64), middle value:0x3a
Byte 2: (0x0c - 0x60), middle value:0x36
Byte 3: (0x14 - 0x68), middle value:0x3e
Byte 4: (0x18 - 0x6c), middle value:0x42
Byte 5: (0x0c - 0x60), middle value:0x36
Byte 6: (0x14 - 0x64), middle value:0x3c
Byte 7: (0x10 - 0x68), middle value:0x3c

MMDC0 MPRDDLCTL = 0x3E363A3A, MMDC1 MPRDDLCTL = 0x3C3C3642

Starting Write calibration...

ABS_OFFSET=0x00000000        result[00]=0x10111111
ABS_OFFSET=0x04040404        result[01]=0x10111010
...
ABS_OFFSET=0x7C7C7C7C        result[1F]=0x11111111

Byte 0: (0x04 - 0x68), middle value:0x36
Byte 1: (0x0c - 0x68), middle value:0x3a
Byte 2: (0x04 - 0x64), middle value:0x34
Byte 3: (0x08 - 0x64), middle value:0x36
Byte 4: (0x08 - 0x6c), middle value:0x3a
Byte 5: (0x14 - 0x70), middle value:0x42
Byte 6: (0x00 - 0x60), middle value:0x30
Byte 7: (0x14 - 0x70), middle value:0x42

MMDC0 MPWRDLCTL = 0x36343A36,MMDC1 MPWRDLCTL = 0x4230423A


   MMDC registers updated from calibration

   Write leveling calibration
   MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00150015
   MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001A0017
   MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x0014001F
   MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x000D001A


   Read DQS Gating calibration
   MPDGCTRL0 PHY0 (0x021b083c) = 0x02020202
   MPDGCTRL1 PHY0 (0x021b0840) = 0x02020202
   MPDGCTRL0 PHY1 (0x021b483c) = 0x01420202
   MPDGCTRL1 PHY1 (0x021b4840) = 0x0202015D


   Read calibration
   MPRDDLCTL PHY0 (0x021b0848) = 0x3E363A3A
   MPRDDLCTL PHY1 (0x021b4848) = 0x3C3C3642


   Write calibration
   MPWRDLCTL PHY0 (0x021b0850) = 0x36343A36
   MPWRDLCTL PHY1 (0x021b4850) = 0x4230423A


Success: DDR calibration completed!!!

The DDR stress test can run with an incrementing frequency or at a static freq
To run at a static freq, simply set the start freq and end freq to the same value
Would do you want run DDR Stress Test? Type 'y' to run and 'n' to skip

Enter desired START freq (135 to 672 MHz), then hit enter.
Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.
420
  The freq you entered was: 420

Enter desired END freq (135 to 672 MHz), then hit enter.
Make sure this is equal to or greater than start freq
500
  The freq you entered was: 500

Do you want to run DDR Stress Test for simple loop or Over Night Test?
Type '0' for simple loop. Type '1' for Over Night Test

DDR Stress Test Iteration 1
Current Temperature: 48
============================================

DDR Freq: 413 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

我根据以上结果，修改flash_header.S文件如下内容
#else /* i.MX6DL 64BIT-DDR */
dcd_hdr:          .word 0x40A002D2 /* Tag=0xD2, Len=83*8 + 4 + 4, Ver=0x40 */
write_dcd_cmd:    .word 0x049C02CC /* Tag=0xCC, Len=83*8 + 4, Param=0x04 */

# IOMUXC_BASE_ADDR  = 0x20e0000
# DDR IO TYPE
MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000)
MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000)
# Clock
MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030)
MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030)
# Address
MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030)
MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030)
MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
# Control
MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x00000030)

MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)

MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4b4, 0x00000030)
MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4b8, 0x00000030)
MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
# Data Strobe
MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00020000)

MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4bc, 0x00000030)
MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4c0, 0x00000030)
MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4c4, 0x00000030)
MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c8, 0x00000030)
MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4cc, 0x00000030)
MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4d0, 0x00000030)
MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4d4, 0x00000030)
MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d8, 0x00000030)

MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x760, 0x00020000)

MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x764, 0x00000030)
MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x770, 0x00000030)
MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x778, 0x00000030)
MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x77c, 0x00000030)
MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x780, 0x00000030)
MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x748, 0x00000030)

MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x470, 0x00000030)
MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x474, 0x00000030)
MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x478, 0x00000030)
MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x47c, 0x00000030)
MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x480, 0x00000030)
MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x484, 0x00000030)
MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x488, 0x00000030)
MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x48c, 0x00000030)

# MMDC_P0_BASE_ADDR = 0x021b0000
# MMDC_P1_BASE_ADDR = 0x021b4000
# Calibrations
# ZQ
MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)

# write leveling
MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x00150015)
MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001A0017)
MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x0014001F)
MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x000D001A)
# DQS gating, read delay, write delay calibration values
# based on calibration compare of 0x00ffff00
MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x02020202)
MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x02020202)
MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83C, 0x01420202)
MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x0202015D)


MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x3E363A3A)
MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x3C3C3642)


MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x36343A36)
MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x4230423A)



修改完毕重新编译后，放入MfgTool2.exe 程序的LINUX\Profiles\MX6Q Linux Update\OS Firmware\mx6_q目录，重新烧录板子，可是uboot启动画面依然显示ddr3为528Mhz，我这样是哪里错了啊，为什么还是改不了ddr3的频率啊……
CPU: Freescale i.MX6 family TO1.2 at 792 MHz
Thermal sensor with ratio = 174
Temperature:   35 C, calibration data 0x54f4ce69
mx6q pll1: 792MHz
mx6q pll2: 528MHz
mx6q pll3: 480MHz
mx6q pll8: 50MHz
ipg clock     : 66000000Hz
ipg per clock : 66000000Hz
uart clock    : 80000000Hz
cspi clock    : 60000000Hz
ahb clock     : 132000000Hz
axi clock   : 264000000Hz
emi_slow clock: 132000000Hz
ddr clock     : 528000000Hz
usdhc1 clock  : 198000000Hz
usdhc2 clock  : 198000000Hz
usdhc3 clock  : 198000000Hz
usdhc4 clock  : 198000000Hz
nfc clock     : 24000000Hz


恳请大佬指点迷津……

我知道答案 目前已有1人回答

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小智MM

你板子上跑的是哪个版本的BSP？