iMX6ULL的PWM在启动后仿真暂停时无法暂停输出

LuoHG

40.4.1.4 Debug Mode Behavior
In debug mode, PWM has the option of continuing to run or be halted. If the DBGEN bit
is not set in the PWM_PWMCR, the PWM is halted. If the DBGEN bit is set, then the
PWM will continue to run in the debug mode.
    pwmConfig.enableStopMode = false;
    pwmConfig.enableDozeMode = false;
    pwmConfig.enableWaitMode = false;
    pwmConfig.enableDebugMode = false;

DBGEN位清0了，通过J-Link仿真器暂停程序执行时，PWM仍在执行输出无法halt。

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LuoHG

stm1024 发表于 2021-8-14 22:52
PWM的时钟脉冲来源是哪里啊？

SDK_2.2_MCIM6ULL\devices\MCIMX6Y2\drivers\fsl_pwm.h中有关时钟源定义确实存在BUG，
原定义
/*! @brief PWM clock source select. */
typedef enum _pwm_clock_source
{
    kPWM_PeripheralClock = 0U,  /*!< The Peripheral clock is used as the clock */
    kPWM_HighFrequencyClock,    /*!< High-frequency reference clock is used as the clock */
    kPWM_LowFrequencyClock      /*!< Low-frequency reference clock(32KHz) is used as the clock */
} pwm_clock_source_t;

已改为
/*! @brief PWM clock source select. */
typedef enum _pwm_clock_source
{
    kPWM_NoneClock = 0U,        /*!< Clock is off, --LuoHG add. */
    kPWM_PeripheralClock,       /*!< The Peripheral clock is used as the clock */
    kPWM_HighFrequencyClock,    /*!< High-frequency reference clock is used as the clock */
    kPWM_LowFrequencyClock      /*!< Low-frequency reference clock(32KHz) is used as the clock */
} pwm_clock_source_t;

stm1024

PWM的时钟脉冲来源是哪里啊？

小恩GG

40.4.1.4 Debug Mode Behavior
In debug mode, PWM has the option of continuing to run or be halted. If the DBGEN bit
is not set in the PWM_PWMCR, the PWM is halted. If the DBGEN bit is set, then the
PWM will continue to run in the debug mode.

-->这段描述是在哪个文档？

LuoHG

stm1024 发表于 2021-8-14 22:52
PWM的时钟脉冲来源是哪里啊？

时钟源自于ipg_clk

PWMx_PWMCR[CLKSRC] = 1

Select Clock Source. These bits determine which clock input will be selected for running the counter. After
reset the system functional clock is selected. The input clock can also be turned off if these bits are set to
00. This field value should only be changed when the PWM is disabled
00 Clock is off
01 ipg_clk
10 ipg_clk_highfreq
11 ipg_clk_32k

LuoHG

小恩GG 发表于 2021-8-16 09:57
40.4.1.4 Debug Mode Behavior
In debug mode, PWM has the option of continuing to run or be halted. If ...

摘录自《IMX6ULL参考手册.pdf》的Chapter 40: Pulse Width Modulation(PWM)