【LPC845-BRK板卡试用申请】(八)时钟系统之Clkdump

andeyqi · 发表于 2023-4-26 12:26:55

本帖最后由 andeyqi 于 2023-4-26 12:26 编辑

简介:

Mcu 开发过程中调试驱动经常会遇到驱动不好用，排查问题中的一环是确认时钟状况，因时钟未打开不同的mcu现象还是不同的，我之前遇到过有的mcu会走到hardfault,有的mcu会寄存器无法写入读取的都是0x00000000，之前经常也在想如果有一个工具能dump出来当前的时钟状态及频率信息的话我们就能直接排除是否是时钟的问题，我们今天的主题就是基于 LPC845 根据内部时钟的拓扑结构输出对应外设节点的时钟路由及频率状态信息。

1.实现方式
我验证的板子上是无外部晶振，CPU使用的 mainclk 可以看出mainclk 时钟来源于内部Fro时钟，从图 1.1 可以看出mainclk时钟的生成的依赖关系为 fro_osc->fro->mainclk-pll_>system_clock 图中的fro_osc振荡器经过时钟选择/分频最终给到MCU 的system clock.

图 1.1

上图的时钟路由上主要包含如下三部分内容（本实验未使用PLL如果使用PLL还包含倍频器）：

1代表的时钟源
2代表的时钟源选择
3代表的分频器

LPC845 的SDK 库里提供了CLOCK_GetFreq 接口获取基本的时钟频率，我们只要根据对应的选择器及分频/倍频系数即可计算出对应的频率，同理对应可以递归找到对应的父节点信息直至回溯到根节点。

uint32_t CLOCK_GetFreq(clock_name_t clockName)
{
uint32_t freq;
switch (clockName)
{
case kCLOCK_CoreSysClk:
freq = CLOCK_GetCoreSysClkFreq();
break;
case kCLOCK_MainClk:
freq = CLOCK_GetMainClkFreq();
break;
case kCLOCK_Fro:
freq = CLOCK_GetFroFreq();
break;
case kCLOCK_FroDiv:
freq = CLOCK_GetFroFreq() >> 1U;
break;
case kCLOCK_ExtClk:
freq = CLOCK_GetExtClkFreq();
break;
case kCLOCK_WdtOsc:
freq = CLOCK_GetWdtOscFreq();
break;
case kCLOCK_PllOut:
freq = CLOCK_GetSystemPLLFreq();
break;
case kCLOCK_Frg0:
freq = CLOCK_GetFRG0ClkFreq();
break;
case kCLOCK_Frg1:
freq = CLOCK_GetFRG1ClkFreq();
break;
default:
freq = 0U;
break;
}
return freq;
}

复制代码

2.代码对应

按照上面的梳理我可可以将各时钟节点的的属性封装成一个结构体，然后通过链表将节点对应的父子关系链接到一起即可获取对应时钟节点的拓扑关系,按照时钟节点的属性信息定义时钟节点如下：

typedef struct clock_node
{
const char * name;
const char * muxhelp;
uint32_t rate;
enum clock_node_id id;
uint8_t is_update;
uint8_t parents_num;
uint8_t mux;
struct clock_node * parents[8];
/*clock node ops*/
uint32_t (*get_rate)(struct clock_node * node);
int (*set_rate)(struct clock_node * node,uint32_t rate);
uint8_t (*get_parent)(struct clock_node * node);
rt_list_t list;
}clock_node_t;

复制代码

name:定义节点名称，主要用于打印节点信息时方便查看
muxhelp:打印mux 选择器的帮助信息
rate:对应节点的时钟频率
id:对应节点id,每个节点有唯一的ID信息，结构体的op函数（get_rate/set_rate/get_parent）会根据此ID信息进行获取信息,当前只定义如下节点后续逐步添加完整

enum clock_node_id
{
CLK_NODE_MAIN_CLK = 0,
CLK_NODE_MAIN_CLK_PRE_PLL,
CLK_NODE_FRO,
CLK_NODE_FRO_OSC,
CLK_NODE_SYSTEM,
CLK_NODE_UART0,
CLK_NODE_UART1,
CLK_NODE_CAPT,
CLK_NODE_MAX
};

复制代码

is_update:对应的时钟节点结构体信息是否完成更新
parents_num:对应节点父节点的数量
mux:当前选择的mux index 数值
parents:父节点的指针数组，LPC 845 寄存器的mux 段最大为3bit 此处定义的最大值8
get_rate：获取对应节点的时钟速率方法，可以根据实际情况设置为NULL
set_rate:设置节点对应的时钟速率，本实验主要用于dump 当前的时钟树此函数未使用设置的NULL
get_parent:获取当前节点的父节点信息，并将值更新至mux成员，然后通过parents[mux]获取父节点信息
list：链表节点用于串联时钟path上各节点

如下是本地定义的main_clk 初始化节点：

static clock_node_t main_clk =
{
.name = "main_clk",
.rate = 0xffffffffu,
.id = CLK_NODE_MAIN_CLK,
.parents_num = 2,
.is_update = 0,
.mux = 0xff,
.muxhelp = "0-main_clk_pre_pll 1-SYS PLL 2/3-none",
.parents[0] = &main_clk_pre_pll,
.parents[1] = NULL,
.get_rate = lpc845_get_clock_rate,
.set_rate = NULL,
.get_parent = lpc845_get_parent,
};

我们按照上述结构对时钟系统上的各节点进行定义后更新信息后，然后通过链表串联起来后打印相关信息即可完成clock path 的时钟信息dump，本地添加clkdump 命令用于更新clock node 信息及打印输出，代码如下：

#include "fsl_device_registers.h"
#include "littleshell.h"
#include "fsl_clock.h"
#include "fsl_debug_console.h"
#include "fsl_syscon.h"
#include "rtlist.h"
#include "utilities.h"
enum clock_node_id
{
CLK_NODE_MAIN_CLK = 0,
CLK_NODE_MAIN_CLK_PRE_PLL,
CLK_NODE_FRO,
CLK_NODE_FRO_OSC,
CLK_NODE_SYSTEM,
CLK_NODE_UART0,
CLK_NODE_UART1,
CLK_NODE_CAPT,
CLK_NODE_MAX
};
typedef struct clock_node
{
const char * name;
const char * muxhelp;
uint32_t rate;
enum clock_node_id id;
uint8_t is_update;
uint8_t parents_num;
uint8_t mux;
struct clock_node * parents[8];
/*clock node ops*/
uint32_t (*get_rate)(struct clock_node * node);
int (*set_rate)(struct clock_node * node,uint32_t rate);
uint8_t (*get_parent)(struct clock_node * node);
rt_list_t list;
}clock_node_t;
static uint32_t lpc845_get_main_clk_pre_pll(struct clock_node * node)
{
uint8_t parent = 0xffu;
uint32_t rate = 0x00;
if(node->get_parent)
{
parent = node->get_parent(node);
}
/* 0-FRO 1- External clock 2- Watchdog oscillator 3- FRO_DIV = FRO / 2 */
switch(parent)
{
case 0:
rate = CLOCK_GetFreq(kCLOCK_Fro);
break;
case 1:
rate = CLOCK_GetFreq(kCLOCK_ExtClk);
break;
case 2:
rate = CLOCK_GetFreq(kCLOCK_WdtOsc);
break;
case 3:
rate = CLOCK_GetFreq(kCLOCK_FroDiv);
break;
default:
break;
}
return rate;
}
static uint32_t lpc845_get_fro_clk(struct clock_node * node)
{
uint8_t parent = 0xffu;
uint32_t rate = 0x00;
if(node->get_parent)
{
parent = node->get_parent(node);
}
/* 0-fro_oscout is divided by 2 (normal boot) or 16 (low power boot), depending on FAIM low power boot value.
* 1-FRO clock is direct from FRO oscillator
*/
switch(parent)
{
case 0:
rate = CLOCK_GetFreq(kCLOCK_FroDiv);
break;
case 1:
rate = CLOCK_GetFreq(kCLOCK_Fro);
break;
default:
break;
}
return rate;
}
static uint32_t lpc845_get_uart_clk(struct clock_node * node)
{
uint8_t parent = 0xffu;
uint32_t rate = 0x00;
if(node->get_parent)
{
parent = node->get_parent(node);
}
/* 0-fro_oscout is divided by 2 (normal boot) or 16 (low power boot), depending on FAIM low power boot value.
* 1-FRO clock is direct from FRO oscillator
*/
switch(parent)
{
case 0:
rate = CLOCK_GetFreq(kCLOCK_Fro);
break;
case 1:
rate = CLOCK_GetFreq(kCLOCK_MainClk);
break;
case 2:
rate = CLOCK_GetFreq(kCLOCK_Frg0);
break;
case 3:
rate = CLOCK_GetFreq(kCLOCK_Frg1);
break;
case 4:
rate = CLOCK_GetFreq(kCLOCK_FroDiv);
break;
default:
break;
}
return rate;
}
static uint32_t lpc845_get_capt_clk(struct clock_node * node)
{
uint8_t parent = 0xffu;
uint32_t rate = 0x00;
if(node->get_parent)
{
parent = node->get_parent(node);
}
/* 0-fro_oscout is divided by 2 (normal boot) or 16 (low power boot), depending on FAIM low power boot value.
* 1-FRO clock is direct from FRO oscillator
*/
switch(parent)
{
case 0:
rate = CLOCK_GetFreq(kCLOCK_Fro);
break;
case 1:
rate = CLOCK_GetFreq(kCLOCK_MainClk);
break;
case 2:
rate = CLOCK_GetFreq(kCLOCK_PllOut);
break;
case 3:
rate = CLOCK_GetFreq(kCLOCK_FroDiv);
break;
case 4:
rate = CLOCK_GetFreq(kCLOCK_WdtOsc);
break;
default:
break;
}
return rate;
}
static uint32_t lpc845_get_clock_rate(struct clock_node * node)
{
uint32_t rate = 0u;
switch(node->id)
{
case CLK_NODE_MAIN_CLK:
rate = CLOCK_GetFreq(kCLOCK_MainClk);
break;
case CLK_NODE_MAIN_CLK_PRE_PLL:
rate = lpc845_get_main_clk_pre_pll(node);
break;
case CLK_NODE_FRO:
rate = lpc845_get_fro_clk(node);
break;
case CLK_NODE_FRO_OSC:
rate = CLOCK_GetFreq(kCLOCK_Fro);
break;
case CLK_NODE_SYSTEM:
rate = CLOCK_GetFreq(kCLOCK_CoreSysClk);
break;
case CLK_NODE_UART0:
case CLK_NODE_UART1:
rate = lpc845_get_uart_clk(node);
break;
default:
break;
}
return rate;
}
static uint8_t lpc845_get_parent(struct clock_node * node)
{
uint8_t parent;
switch(node->id)
{
case CLK_NODE_MAIN_CLK:
parent = SYSCON->MAINCLKPLLSEL & 0x03;
break;
case CLK_NODE_MAIN_CLK_PRE_PLL:
parent = SYSCON->MAINCLKSEL & 0x03;
break;
case CLK_NODE_FRO:
parent = (SYSCON->FROOSCCTRL & SYSCON_FROOSCCTRL_FRO_DIRECT_MASK)>>SYSCON_FROOSCCTRL_FRO_DIRECT_SHIFT;
break;
case CLK_NODE_SYSTEM:
parent = 0;
break;
case CLK_NODE_UART0:
parent = SYSCON->FCLKSEL[0] & 0x07;
break;
case CLK_NODE_UART1:
parent = SYSCON->FCLKSEL[1] & 0x07;
break;
case CLK_NODE_CAPT:
parent = SYSCON->CAPTCLKSEL & 0x07;
break;
default:
break;
}
return parent;
}
static clock_node_t fro_osc =
{
.name = "fro_osc",
.rate = 0xffffffffu,
.id = CLK_NODE_FRO_OSC,
.parents_num = 0,
.is_update = 0,
.mux = 0xff,
.muxhelp = NULL,
.get_rate = lpc845_get_clock_rate,
.set_rate = NULL,
.get_parent = NULL,
};
static clock_node_t fro =
{
.name = "fro",
.rate = 0xffffffffu,
.id = CLK_NODE_FRO,
.parents_num = 2,
.is_update = 0,
.mux = 0xff,
.muxhelp = "0:fro_oscout is divided2 1:FRO oscillator",
.parents[0] = NULL,
.parents[1] = &fro_osc,
.get_rate = lpc845_get_clock_rate,
.set_rate = NULL,
.get_parent = lpc845_get_parent,
};
static clock_node_t main_clk_pre_pll =
{
.name = "main_clk_pre_pll",
.rate = 0xffffffffu,
.id = CLK_NODE_MAIN_CLK_PRE_PLL,
.parents_num = 4,
.is_update = 0,
.mux = 0xff,
.muxhelp = "0-FRO 1- External clock 2- Watchdog oscillator 3- FRO_DIV = FRO / 2",
.parents[0] = &fro,
.parents[1] = NULL,
.parents[2] = NULL,
.parents[3] = NULL,
.get_rate = lpc845_get_clock_rate,
.set_rate = NULL,
.get_parent = lpc845_get_parent,
};
static clock_node_t main_clk =
{
.name = "main_clk",
.rate = 0xffffffffu,
.id = CLK_NODE_MAIN_CLK,
.parents_num = 2,
.is_update = 0,
.mux = 0xff,
.muxhelp = "0-main_clk_pre_pll 1-SYS PLL 2/3-none",
.parents[0] = &main_clk_pre_pll,
.parents[1] = NULL,
.get_rate = lpc845_get_clock_rate,
.set_rate = NULL,
.get_parent = lpc845_get_parent,
};
static clock_node_t system_clk =
{
.name = "system_clk",
.rate = 0xffffffffu,
.id = CLK_NODE_SYSTEM,
.parents_num = 1,
.is_update = 0,
.mux = 0xff,
.muxhelp = NULL,
.parents[0] = &main_clk,
.get_rate = lpc845_get_clock_rate,
.set_rate = NULL,
.get_parent = lpc845_get_parent,
};
static clock_node_t uart0_clk =
{
.name = "uart0_clk",
.rate = 0xffffffffu,
.id = CLK_NODE_UART0,
.parents_num = 5,
.is_update = 0,
.mux = 0xff,
.muxhelp = "0-FRO 1-Main clock 2-FRG0 clock 3-FRG1 clock 4-FRO_DIV = FRO / 2 5~7-none",
.parents[0] = &fro,
.parents[1] = &main_clk,
.parents[2] = &fro,
.parents[3] = NULL,
.parents[4] = NULL,
.parents[5] = NULL,
.parents[6] = NULL,
.parents[7] = NULL,
.get_rate = lpc845_get_uart_clk,
.set_rate = NULL,
.get_parent = lpc845_get_parent,
};
static clock_node_t uart1_clk =
{
.name = "uart1_clk",
.rate = 0xffffffffu,
.id = CLK_NODE_UART1,
.parents_num = 5,
.is_update = 0,
.mux = 0xff,
.muxhelp = "0-FRO 1-Main clock 2-FRG0 clock 3-FRG1 clock 4-FRO_DIV = FRO / 2 5~7-none",
.parents[0] = &fro,
.parents[1] = &main_clk,
.parents[2] = &fro,
.parents[3] = NULL,
.parents[4] = NULL,
.parents[5] = NULL,
.parents[6] = NULL,
.parents[7] = NULL,
.get_rate = lpc845_get_uart_clk,
.set_rate = NULL,
.get_parent = lpc845_get_parent,
};
static clock_node_t capt_clk =
{
.name = "capt_clk",
.rate = 0xffffffffu,
.id = CLK_NODE_CAPT,
.parents_num = 5,
.is_update = 0,
.mux = 0xff,
.muxhelp = "0-FRO 1-Main clock 2-SYS PLL 3-FRO_DIV = FRO/2 clock 4-Watchdog oscillator 5~7-none",
.parents[0] = &fro,
.parents[1] = &main_clk,
.parents[2] = NULL,
.parents[3] = NULL,
.parents[4] = NULL,
.parents[5] = NULL,
.parents[6] = NULL,
.parents[7] = NULL,
.get_rate = lpc845_get_capt_clk,
.set_rate = NULL,
.get_parent = lpc845_get_parent,
};
void update_clk_node(struct clock_node * node)
{
if(!node->is_update)
{
if(node->get_rate)
{
node->rate = node->get_rate(node);
}
if(node->get_parent)
{
node->mux = node->get_parent(node);
}
rt_list_init(&node->list);
node->is_update = 1;
}
}
void dump_clk_node(struct clock_node * node)
{
if(node->is_update)
{
PRINTF(".name = %s\r\n",node->name);
PRINTF(".rate = %d\r\n",node->rate);
PRINTF(".id = %d\r\n",node->id);
PRINTF(".parents_num = %d\r\n",node->parents_num);
if(node->parents_num != 0xff && node->parents_num != 0)
PRINTF("%s parent id is %d\r\n",node->muxhelp,node->mux);
}
else
{
PRINTF("%s node need update info.\r\n",node->name);
}
}
void trace_clk_node(struct clock_node * node)
{
rt_list_t head = RT_LIST_OBJECT_INIT(head);
rt_list_t * pos;
struct clock_node * p_node = node;
uint8_t i_loop = 0;
const char * root_clk[10] = {
"|-- ",
"| |-- ",
"| | |-- ",
"| | | |-- ",
"| | | | |-- ",
"| | | | | |-- ",
"| | | | | | |-- ",
"| | | | | | | |-- ",
"| | | | | | | | |-- ",
"| | | | | | | | | |-- ",
};
do
{
update_clk_node(p_node);
rt_list_insert_after(&head,&p_node->list);
if(p_node->parents_num)
p_node = p_node->parents[p_node->mux];
}while(p_node && p_node->parents_num);
if(p_node)
{
update_clk_node(p_node);
rt_list_insert_after(&head,&p_node->list);
}
PRINTF("\r\n\r\n");
rt_list_for_each(pos,&head)
{
p_node = rt_list_entry(pos, clock_node_t, list);
PRINTF("%s *%s\r\n",root_clk[i_loop],p_node->name);
PRINTF("%s [rate]%d\r\n",root_clk[i_loop+1],p_node->rate);
if(p_node->muxhelp)
PRINTF("%s [%s]:[%d]\r\n",root_clk[i_loop+1],p_node->muxhelp,p_node->mux);
i_loop++;
}
}
unsigned int clkdump(char argc,char ** argv)
{
uint8_t index = atoi(argv[1]);
switch(index)
{
case 0:
dump_clk_node(&main_clk);
update_clk_node(&main_clk);
dump_clk_node(&main_clk);
break;
case 1:
dump_clk_node(&main_clk_pre_pll);
update_clk_node(&main_clk_pre_pll);
dump_clk_node(&main_clk_pre_pll);
break;
case 2:
dump_clk_node(&fro);
update_clk_node(&fro);
dump_clk_node(&fro);
break;
case 3:
dump_clk_node(&fro_osc);
update_clk_node(&fro_osc);
dump_clk_node(&fro_osc);
break;
case 4:
trace_clk_node(&system_clk);
break;
case 5:
trace_clk_node(&uart0_clk);
break;
case 6:
trace_clk_node(&uart1_clk);
break;
case 7:
trace_clk_node(&capt_clk);
break;
default:
break;
}
return 1;
}
LTSH_FUNCTION_EXPORT(clkdump,"dump clk info");