[求助]MPC5554移植操作系统报错~求救

carthor

小弟最近在对MPC5554EVB开发板进行uC/OS进行操作系统移植，开发环境用的是CodeWarrior for MPC55xx V2.3，代码应该没有问题，编译也通过了，但是执行“make”的时候老是报错，报错如下：
Link Error:Can't write binary file 'OS.bin'
because gap between bin file offset for segment .bss and .data wasn't updated correstly(too much)
internal linker error:'ELF_gen.c' Line:3922
不晓得 codewarrior哪里设置错了，期待达人解答，万分感谢！
小弟QQ:19626106，邮箱用的也是QQ的邮箱：19626106@qq.com

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carthor

再贴上LCF文件，高手过来看看应该怎么修改呀~
MEMORY
{
/* 2M External Flash (unused) */
/* 512K External SRAM (unused) */
        ext_flash : org = 0x20000000, len = 0x00200000
        ext_ram   : org = 0x3ff80000, len = 0x80000
/* Internal Flash RCW */
/* MPC5554 2M Internal Flash, but subtract one 128K block for use by BAM. */
/* MPC5554 64K Internal SRAM */
/* MPC5554 4K of internal cache used for stack. */
        flash_rcw : org = 0x00000000, len = 0x8
        int_flash : org = 0x00000008, len = 0x001FFFF8
        int_sram  : org = 0x40000000, len = 0x10000
        stack_ram : org = 0x40040000, len = 0x1000
}

SECTIONS
{
/* ROM data */
    .rcw  : { *(.rcw) } > flash_rcw
  GROUP : {
    .init       : { *(.init) }
    .text       : {}
    .flash_data : {}
    .rodata  : {
         *(.rdata)
         *(.rodata)
       }
    .ctors : {}
    .dtors : {}
/* Exception table IVPR register must align on a 16-bit boundary */
/*  RAM is from 0x4000_0000 to 0x4000_FFFF; IVPR upper 16-bits   */
/*  must align to 0x4000_xxxx for internal SRAM                  */
/*     So "ALIGN(0x10000) has been removed from .xcptn for SRAM  */
    .xcptn     ALIGN(0x100) : {}
     extabindex : {}
     extab      : {}
      /* align __DATA_ROM to .data start */
     __DATA_ROM = (. + 7) & ~7;
  } > int_flash

/* SRAM data */
    GROUP :
    {
        .data   LOAD(  __DATA_ROM): {}
       
        PROVIDE(__SDATA_ROM =(__DATA_ROM + SIZEOF(.data) + 7) & ~7);
        .sdata  LOAD( __SDATA_ROM): {}
        .sbss   : {}
       
        PROVIDE(__SDATA2_ROM = (__SDATA_ROM + SIZEOF(.sdata) + 7) & ~7);
        .sdata2 LOAD(__SDATA2_ROM): {}
        .sbss2  : {}
        .isrvectbl ALIGN(0x800) : {}
        .bss    : {}  
        .heap   : {}
    } > int_sram
/* Stack area */
    .stack  : {} > stack_ram
/* Stack Address Parameters */
__SP_INIT      = ADDR(stack_ram) + SIZEOF(stack_ram);
__SP_END       = ADDR(stack_ram);
__STACK_SIZE   = SIZEOF(stack_ram);
/* SRAM Address Parameters */
__SRAM_CPY_START  = ADDR(.data);
__ROM_COPY_SIZE   = (SIZEOF(.data) + SIZEOF(.sdata));
__SRAM_CPY2_START = ADDR(.sdata2);
__ROM_COPY2_SIZE  = SIZEOF(.sdata2);
__SRAM_LOAD      = ADDR(.heap);
__SRAM_LOAD_SIZE = (SIZEOF(.flash_data)/4);
/* The EABI defines the location of _SDA_BASE_ and _SDA2_BASE_  */
/*  cfg_PNTRS places _SDA_BASE_ into R13 and _SDA2_BASE into R2 */
/*_SDA_BASE_ = ADDR(.sdata) + 0x8000 (+0x7FF0 for WindRiver)    */
/*_SDA2_BASE_ = ADDR(.sdata2) + 0x8000 (+0x7FF0 for WindRiver)  */
/* Interrupt Handler Parameters */
__IV_ADDR      = ADDR(.xcptn);
}
/* FORCEFILES are used so that the linker will not deadstrip  */
/* the functions and variables which are not initially used   */
/* in the program. Examples included here are parts of the    */
/* exception, interrupt routines.                             */
FORCEACTIVE { }
/* Metrowerks Code Warrior compiler address designations */
_stack_addr = ADDR(stack_ram)+SIZEOF(stack_ram);
_stack_end = ADDR(stack_ram);
_heap_addr = ADDR(.bss)+SIZEOF(.bss);
_heap_end = ADDR(int_sram)+SIZEOF(int_sram);
_init_addr = ADDR(.init);
_init_end = ADDR(.init)+SIZEOF(.init);