【MIMXRT1060-EVK+RT-Thread】艰难的起步之路

morphlings2014 · 发表于 2023-7-6 18:40:11

本帖最后由 morphlings2014 于 2023-7-6 18:42 编辑

本次使用的开发板是 MIMXRT1060-EVK 版本，套件包含了 MIMXRT1060-EVK评估板、USBx线缆（Micro B）、摄像头传感器模块

板卡资料

板卡的资料都可以在 i.MX RT1060评估套件 | NXP 半导体找到，但是相较于收到的版本，和官网提供的设计文件有些出入

官网版本代码存储的 flash 默认连接的是 QSPI Flash ，而我收到的版本默认连接的是 HyperFlash，也是看了论坛大佬们的帖子才发现的，大佬牛哔

RT-Thread 资料

源码地址 rt-thread.org/download.html#download-rt-thread-source-code
ENV 工具地址 rt-thread.org/download.html#download-rt-thread-env-tool
文档中心 RT-Thread 文档中心

构建工程

代码目录 rt-thread\bsp\imxrt\imxrt1060-nxp-evk，已经有对应的 bsp，可以直接打开 keil 工程可能会报错，建议使用 scons 工具同步下 scons --target=mdk5

> scons --target=mdk5
scons: Reading SConscript files ...
Keil5 project is generating...
Keil Version: 0.0
Keil-MDK project has generated successfully!

打开工程，需要替换 evkmimxrt1060_flexspi_nor_config.c 文件的配置信息，默认用的是 QSPI Flash

替换内容可以参考 MIMXRT1050 目录下的配置文件，具体信息如下：

const flexspi_nor_config_t hyperflash_config =
{
.memConfig =
{
      .tag = FLEXSPI_CFG_BLK_TAG,
      .version = FLEXSPI_CFG_BLK_VERSION,
      .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
      .csHoldTime = 3u,
      .csSetupTime = 3u,
      .columnAddressWidth = 3u,
      // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
      .controllerMiscOption = (1u << kFlexSpiMiscOffset_DdrModeEnable) |
                              (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
                              (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) |
                              (1u << kFlexSpiMiscOffset_DiffClkEnable),
      .deviceType = kFlexSpiDeviceType_SerialNOR,
      .sflashPadType = kSerialFlash_8Pads,
      .serialClkFreq = kFlexSpiSerialClk_133MHz,
      .lutCustomSeqEnable = 0x1,
      .sflashA1Size = 64u * 1024u * 1024u,
      .dataValidTime = {15u, 0u},
      .busyOffset = 15u,
      .busyBitPolarity = 1u,
      .lookupTable =
      {
         // Read LUTs
         [0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
         [1] = FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x0C),
         [2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),

         // Read Status LUTs
         // 0
         [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
         [4 * 1 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
         [4 * 1 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
         [4 * 1 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x70),

         // 1
         [4 * 2 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
         [4 * 2 + 1] =
            FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_RWDS_DDR, FLEXSPI_8PAD, 0x0B),
         [4 * 2 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x4, STOP, FLEXSPI_1PAD, 0x0),

         // Write Enable LUTs
         // 0
         [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
         [4 * 3 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
         [4 * 3 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
         [4 * 3 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),

         // 1
         [4 * 4 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
         [4 * 4 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x55),
         [4 * 4 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x02),
         [4 * 4 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x55),

         // Erase Sector LUTs
         // 0
         [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
         [4 * 5 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
         [4 * 5 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
         [4 * 5 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x80),

         // 1
         [4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
         [4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
         [4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
         [4 * 6 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),

         // 2
         [4 * 7 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
         [4 * 7 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x55),
         [4 * 7 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x02),
         [4 * 7 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x55),

         // 3
         [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
         [4 * 8 + 1] = FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, CMD_DDR, FLEXSPI_8PAD, 0x0),
         [4 * 8 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x30, STOP, FLEXSPI_1PAD, 0x0),

         // Page Program LUTs
         // 0
         [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
         [4 * 9 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
         [4 * 9 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
         [4 * 9 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xA0),

         // 1
         [4 * 10 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
         [4 * 10 + 1] =
            FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, WRITE_DDR, FLEXSPI_8PAD, 0x80),

         // Erase Chip LUTs
         // 0
         [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
         [4 * 11 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
         [4 * 11 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
         [4 * 11 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x80),

         // 1
         [4 * 12 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
         [4 * 12 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
         [4 * 12 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
         [4 * 12 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),

         // 2
         [4 * 13 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
         [4 * 13 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x55),
         [4 * 13 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x02),
         [4 * 13 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x55),

         // 3
         [4 * 14 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
         [4 * 14 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
         [4 * 14 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
         [4 * 14 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x10),
      },
      // LUT customized sequence
      .lutCustomSeq =
      {
         {
               .seqNum = 0,
               .seqId = 0,
               .reserved = 0,
         },
         {
               .seqNum = 2,
               .seqId = 1,
               .reserved = 0,
         },
         {
               .seqNum = 2,
               .seqId = 3,
               .reserved = 0,
         },
         {
               .seqNum = 4,
               .seqId = 5,
               .reserved = 0,
         },
         {
               .seqNum = 2,
               .seqId = 9,
               .reserved = 0,
         },
         {
               .seqNum = 4,
               .seqId = 11,
               .reserved = 0,
         }
      },
},
.pageSize = 512u,
.sectorSize = 256u * 1024u,
.ipcmdSerialClkFreq = 1u,
.serialNorType = 1u,
.blockSize = 256u * 1024u,
.isUniformBlockSize = true,
};

编译之后 cpu_cache.c 还可能有错误，增加对应的头文件，即可

添加下载算法，需要先安装 NXP.MIMXRT1052_DFP.16.0.0.pack 的开发包，然后在 Pack 的安装目录下找到对应的算法

拷贝至 KEIL 安装目录下的 ARM\Flash 文件夹下，之后就能再添加界面选择对应的算法

编译下载，可以看到终于运行起来了

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