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一、简介
上个月一直疯狂的想拥有一块LPC55S69-EVK,一方面LPC这颗MCU功能强大,另一方面之前一直玩STM32,想体验下不同风格~于是在管管大喜假期结束回来上班的那天,跟他达成了一个交易~最终拿到了梦寐以求的LPC55S69-EVK。就这个,感谢管管,盒子很大,板子比想象中的小,很精致。
二、MCU版本
拿到的板子是LPC55S69-EVK的A1版,也就是说后续还有A2和A3版,据说后面的版本MCU功能更强大,可以实现一些多媒体应用,譬如接上USB camera拍照。A1版本开发板的区别主要在于MCU,NXP官方给出的信息:
At the time of the latest update to this article, the latest silicon revision of the LPC55S6x is revision 1B. Since Nov,2019, all the LPCXpresso55S69 EVK boards marked as Revision A2 or A3 are equipped with revision 1B silicon. Initial production boards that have 0A silicon installed are marked Revision A1. 也就是说2019年11月之后的LPC55S69都是改良版的MCU,with revision 1B silicon,频率150MHZ,手头的的A1 LPC55S69-EVK的MCU是0A版,只有100MHZ,其它功能上的区别如debug的重新设计我也不管了,反正一下子用不上,这运行频率相差一半了,必须想想办法补回来。
三、100MHZ配置
直接贴时钟配置源码:
- POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
- CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
- CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
- CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
- POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
- POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
- CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
- SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
- ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
- POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
- CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
- /*!< Set up PLL */
- CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
- POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
- POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
- const pll_setup_t pll0Setup = {
- .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(54U) | SYSCON_PLL0CTRL_SELP(26U),
- .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
- .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
- .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
- .pllRate = 100000000U,
- .flags = PLL_SETUPFLAG_WAITLOCK
- };
- CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
- /*!< Set up dividers */
- CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
- /*!< Set up clock selectors - Attach clocks to the peripheries */
- CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
复制代码
四、150MHZ配置
还是直接上源码:
- POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
- CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
- CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
- POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
- POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
- CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
- SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
- ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
- POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
- CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
- /*!< Set up PLL */
- CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
- POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
- POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
- const pll_setup_t pll0Setup = {
- .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
- .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
- .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
- .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
- .pllRate = 150000000U,
- .flags = PLL_SETUPFLAG_WAITLOCK
- };
- CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
- /*!< Set up dividers */
- CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
- /*!< Set up clock selectors - Attach clocks to the peripheries */
- CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
复制代码
五,测试
配置好后,需要测试下100MHZ跟150MHZ到底啥区别。引入COREMARK来测试下,在相同的编译和执行环境下,只改变MCU的运行频率。
(一)100MHZ成绩
The CPU frequency is: 100000000 Hz
Benchmark started, please make sure it runs for at least 10s.
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 82403
Total time (secs): 82.403000
Iterations/Sec : 43.687730
Iterations : 3600
Compiler version : GCCClang 15.0.0
Compiler flags :
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0x5275
Correct operation validated. See README.md for run and reporting rules.
CoreMark 1.0 : 43.687730 / GCCClang 15.0.0 / STACK
(二)150MHZ成绩
The CPU frequency is: 150000000 Hz
Benchmark started, please make sure it runs for at least 10s.
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 63474
Total time (secs): 63.474000
Iterations/Sec : 56.716136
Iterations : 3600
Compiler version : GCCClang 15.0.0
Compiler flags :
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0x5275
Correct operation validated. See README.md for run and reporting rules.
CoreMark 1.0 : 56.716136 / GCCClang 15.0.0 / STACK 六、结论
150MHZ的MCU测试耗时63.474s,coremark成绩为56.716136;相较100MHZ的测试耗时82.403s,coremark成绩43.68773,提升巨大!
说明0A silicon是可以运行在150MHZ的频率,并且性能提升巨大。
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