求教关于PLL作为时钟源的问题（已解决）

tovax · 发表于 2014-10-9 11:29:04

本帖最后由 tovax 于 2014-10-11 17:05 编辑

初始化PLL的最后阶段有如下语句：

//Now in PBE
//Clear CLKS to switch CLKS mux to select PLL as MCG_OUT
MCG_C1 &= ~MCG_C1_CLKS_MASK;
//Wait for clock status bits to update
for(i = 0 ; i < 2000 ; i++)
{
//Jump out early if CLKST = 3 before loop finishes
if(((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) == 0x3) break;
}
//Check CLKST is set correctly and return with error if not
if(((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3) return 0x1B;
//Now in PEE

复制代码

仿真发现，在"if(((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) == 0x3) break;"处程序跑飞了。
飞到这句代码的前边几句，然后再执行到这里，再跑飞，这样死循环。。。

屏蔽掉“MCG_C1 &= ~MCG_C1_CLKS_MASK;”这句之后，程序不会跑飞，但是PLL初始化不成功了，一直从“return 0x1B”处退出。

调用的官方代码 ( KINETIS512_V2_SC ) ：

/* Set the system dividers */
/* NOTE: The PLL init will not configure the system clock dividers,
* so they must be configured appropriately before calling the PLL
* init function to ensure that clocks remain in valid ranges.*/
SIM_CLKDIV1 = ( 0
| SIM_CLKDIV1_OUTDIV1(0)
| SIM_CLKDIV1_OUTDIV2(1)
| SIM_CLKDIV1_OUTDIV3(1)
| SIM_CLKDIV1_OUTDIV4(3) );
/* Initialize PLL */
/* PLL will be the source for MCG CLKOUT so the core, system, and flash clocks are derived from it */
mcg_clk_hz = pll_init(CLK0_FREQ_HZ, /* CLKIN0 frequency */
LOW_POWER, /* Set the oscillator for low power mode */
CLK0_TYPE, /* Crystal or canned oscillator clock input */
PLL0_PRDIV, /* PLL predivider value */
PLL0_VDIV, /* PLL multiplier */
MCGOUT); /* Use the output from this PLL as the MCGOUT */
/* Check the value returned from pll_init() to make sure there wasn't an error */
if (mcg_clk_hz < 0x100) while(1);

复制代码

我的宏定义如下：
#define CLK0_FREQ_HZ 12000000
#define CLK0_TYPE CRYSTAL
#define LOW_POWER 0
#define HIGH_GAIN 1
#define PLL0_PRDIV 6
#define PLL0_VDIV 25
#define PLL_ONLY 0
#define MCGOUT 1
#define CANNED_OSC 0
#define CRYSTAL 1

SOC：MK10DN512VLQ10

请问这是怎么回事呢？

我知道答案目前已有18人回答

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